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LT1990CS8 Datasheet(PDF) 7 Page - Linear Technology |
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LT1990CS8 Datasheet(HTML) 7 Page - Linear Technology |
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7 / 16 page ![]() LT1990 7 1990f SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ∆G Gain Error VOUT = ±10V LT1990, G = 1 ● 0.67 % LT1990A, G = 1 ● 0.35 % G = 10 ● 0.9 % GNL Gain Nonlinearity VOUT = ±10V G = 1 ● 0.003 % G = 10 ● 0.03 % G/T Gain vs Temperature G = 1 (Note 10) ● 2 10 ppm/°C G = 10 (Note 10) ● 7 20 ppm/°C VCM Input Voltage Range Guaranteed by CMRR ● –250 250 V CMRR Common Mode Rejection Ratio, RTI VCM = –250V to 250V LT1990 ● 58 dB LT1990A ● 67 dB VOS Input Offset Voltage, RTI G = 1, 10 ● 6.7 mV VOS/T Input Offset Voltage Drift, RTI (Note 10) ● 522 µV/°C VOSH Input Offset Voltage Hysteresis, RTI (Note 11) ● 250 µV PSRR Power Supply Rejection Ratio, RTI VS = ±1.35V to ±18V ● 78 dB Minimum Supply Voltage Guaranteed by PSRR ● ±1.35 V IS Supply Current 280 µA VOUT Output Voltage Swing ● ±14.3 V ISC Output Short-Circuit Current Short to V– ● 3mA Short to V+ ● 10 mA SR Slew Rate G = 1, VOUT = ±10V ● 0.2 V/µs Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: ESD (Electrostatic Discharge) sensitive device. Extensive use of ESD protection devices are used internal to the LT1990, however, high electrostatic discharge can damage or degrade the device. Use proper ESD handling precautions. Note 3: A heat sink may be required to keep the junction temperature below absolute maximum. Note 4: The LT1990C/LT1990I are guaranteed functional over the operating temperature range of – 40°C to 85°C. Note 5: The LT1990C is guaranteed to meet the specified performance from 0°C to70°C and is designed, characterized and expected to meet specified performance from –40°C to 85°C but is not tested or QA sampled at these temperatures. The LT1990I is guaranteed to meet specified performance from –40°C to 85°C. Note 6: G = 10 limits are guaranteed by correlation to G = 1 tests and gain error tests at G = 10. Note 7: Limits are guaranteed by correlation to –5V to 80V CMRR tests. Note 8: VS = 3V limits are guaranteed by correlation to VS = 5V and VS = ±15V tests. Note 9: VS = 5V limits are guaranteed by correlation to VS = 3V and VS = ±15V tests. Note 10: This parameter is not 100% tested. Note 11: Hysteresis in offset voltage is created by package stress that differs depending on whether the IC was previously at a higher or lower temperature. Offset voltage hysteresis is always measured at 25°C, but the IC is cycled to 85°C I-grade (or 70°C C-grade) or –40°C I-grade (0°C C-grade) before successive measurement. ±15V ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the temperature range of –40°C ≤ TA ≤ 85°C. VS = ±15V, RL = 10k, VCM = VREF = 0V, G = 1, 10, unless otherwise noted. (Notes 4, 6) |
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