High Speed CMOS Logic – 54HC138

Rev 1.0

23/11/17

 

3-Line to 8-Line Decoder / Demultiplexer in bare die form

 

 

Output Drive Capability: 10 LSTTL Loads

Low Input Current: 1µA

Outputs directly interface CMOS, NMOS and TTL

 

 

Operating Voltage Range: 2V to 6V

CMOS High Noise Immunity

 

Function compatible with 54LS138

 

Full Military Temperature Range.

 

 

 

Features:

Ordering Information

The 54HC138 is fabricated using a 2.5µm 5V CMOS

process with the same high speed performance of LSTTL

combined with CMOS low power consumption. Inputs are

compatible with standard CMOS outputs and LSTTL

outputs by using pull-up resistors. The device decodes a

three–bit Address to one–of–eight active–low outputs.

Featuring three Chip Select inputs, two active–low & one

active–high to facilitate the demultiplexing, cascading, and

chip–selecting functions. The demultiplexing function uses

the Address inputs to select desired device output; one of

the Chip Selects is used as a data input while the other

Chip Selects are held in their active states.

Description

Die Dimensions in µm (mils)

 

The following part suffixes apply:

1450 (57)

 

No suffix - MIL-STD-883 /2010B Visual Inspection

 

“H” - MIL-STD-883 /2010B Visual Inspection

+ MIL-PRF-38534 Class H LAT

 

 

“K” - MIL-STD-883 /2010A Visual Inspection (Space)

+ MIL-PRF-38534 Class K LAT

LAT = Lot Acceptance Test.

 

 

For more information on LAT flows please see below.

www.siliconsupplies.com\quality\bare-die-lot-qualification

 

 

Die Size (Unsawn)

1450 x 1500

57 x 59

µm

 

 

 

 

mils

Minimum Bond Pad Size

100 x 100

4 x 4

µm

mils

Die Thickness

350 (±20)

13.78 (±0.79)

µm

mils

Supply Formats:

Mechanical Specification

Default – Die in Waffle Pack (400 per tray capacity)

Sawn Wafer on Tape – On request

Unsawn Wafer – On request

Die Thickness <> 350µm(14 Mils) – On request

Top Metal Composition

Al 1%Si 1.1µm

Back Metal Composition

N/A – Bare Si

Assembled into Ceramic Package – On request

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