FP6861C datasheet(13/16 Pages) FITIPOWER

13 / 16 page

FP6861C-1.0-DEC-2015

FP6861C

Application Information (Continued)

Supply Filter/Bypass Capacitor

The input capacitor must be at least

1μF low-ESR

ceramic capacitor connected from VIN to GND, but

can be increased without limit.

Output short may

cause sufficient ringing on the input (from source

lead inductance) to destroy the internal control

circuitry.

The input transient must not exceed 6V of

the absolute maximum supply voltage even for a

short duration.

Output Filter Capacitor

Output is recommended to use a 22

μF ceramic

capacitor in parallel with a 100

μF electrolytic

capacitor.

Standard bypass methods should be

used to minimize inductance and resistance between

the bypass capacitor and the downstream connector

which reduce EMI and decouple voltage drop caused

when

downstream

cables

are

hot-insertion

transients.

Ferrite beads in series with VBUS, the

ground line and the 0.1μF bypass capacitors at the

power connector pins are recommended for EMI and

ESD protection.

The bypass capacitor should have

a low dissipation factor to allow decoupling at higher

frequencies.

Power Dissipation

The device’s junction temperature depends on

several factors, such as the load, PCB layout,

ambient

temperature

and

package

type.

However, the maximum output current must be

decreased at higher ambient temperature to ensure

the junction temperature does not exceed 150°C.

With all possible conditions, the junction temperature

must be within the range specified under operating

conditions.

Power dissipation can be calculated

based on the output current and the RDS(ON) of switch

as below:

=R S(O )

OUT

Although the devices are rated by current limit, but

the application may limit the amount of output current

based on the total power dissipation and the ambient

temperature.

The

final

operating

junction

temperature for any set of conditions can be

estimated by the following thermal equation:

(MA ) =

T (MA ) TA

θ A

where TJ(MAX) is the maximum junction temperature

125°C, TA is the ambient temperature and the θJA is

the junction to ambient thermal resistance.

The junction to ambient thermal resistance θ

JA is

related to layout.

For SOT-23-5 package, the

therma

l resistance θ

JA is 250°C/W on the standard

JEDEC 51-3 single-layer thermal test board.

PCB Layout

In order to meet the voltage drop and EMI

requirements, careful PCB layout is necessary.

The following guidelines must be considered:

1. Keep all VBUS traces as short as possible, and

use at least 50-mil and 2 ounce copper for all

VBUS traces.

2. Locate the FP6861C as close to the output port

as possible to limit switching noise.

3. Locate the ceramic bypass capacitors as close

to the VIN pins of the FP6861C as possible.

4. Avoid vias as much as possible.

If vias are

necessary, make them as large as feasible.

5. Place a ground plane under all circuitry to lower

both resistance and inductance, and improve

DC and transient performance (use a separate

ground and power plans if possible).

6. Place cuts in the ground plane between ports to

help

reducing

the

coupling

transients

between ports.

7. Locate the output capacitor and ferrite beads as

close to the USB connectors as possible to

lower impedance (mainly inductance) between

the port and the capacitor, and improve

transient load performance.

FP6861C Datasheet(PDF) 13 Page - Fitipower Integrated Technology Inc.

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