13

FP9928A-0.1-OCT-2013

FP9928A

fitipower integrated technology lnc.

I

Serial Interface

The serial interface is compatible with the standard and fast mode I

400 kHz.

The interface adds flexibility to the power supply solution, enabling most functions to be

programmed to new values depending on the instantaneous application requirements and the PMIC status to

be monitored.

The E Ink® PMIC has a 7bit address: ‘1001000’, other addresses are available upon contact

with the factory.

Attempting to read data from register addresses not listed in this section will result in 00h

being read out.

For normal data transfer, SDA is allowed to change only when SCL is low.

Changes when

SCL is high are reserved for indicating the start and stop conditions.

During data transfer, the data line must

remain stable whenever the clock line is high.

There is one clock pulse per bit of data.

Each data transfer is

initiated with a start condition and terminated with a stop condition.

When addressed, the

–PMIC generates

an acknowledge bit after the reception of each byte.

The master device (microprocessor) must generate an

extra clock pulse that is associated with the acknowledge bit.

The

–PMIC will pull down the SDA line during

the acknowledge clock pulse so that the SDA line is a stable low during the high period of the acknowledge

clock pulse.

The SDA line is a stable low during the high period of the acknowledge

–related clock pulse.

Setup and hold times must be taken into account.

During read operations, a master must signal the end of

data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this

case, the slave

–PMIC device must leave the data line high to enable the master to generate the stop

condition.

DATA

CLK

Data line

stable;

data valid

Change

of data

allowed

Figure 9. bit transfer on the serial interface

DATA

CLK

S

START condition

P

STOP condition

Figure 10. START and STOP conditions