Digital Inputs

MCLK - Master Clock, Pin 7.

Clock source for the delta-sigma modulator sampling and digital filters.

In Master Mode, the frequency of this clock must be 256

× the output sample rate, Fs.

In Slave Mode, the frequency of this clock must be either 256

×, 384× or 512× Fs.

DIF0, DIF1 - Digital Interface Format, Pins 19 and 20.

These two pins select one of 3 digital interface formats or power-down. The format determines

the relationship between SCLK, LRCK and SDATA. The formats are detailed in Figures 3-5.

RST - Reset, Pin 18.

A low logic level on this pin activates Reset.

HP DEFEAT - High Pass Filter Defeat, Pin 1.

A high logic level on this pin disables the digital high pass filter. A low logic level on this pin

enables the high pass filter.

PU - Peak Update, Pin 11.

Transfers the Peak Signal Level contents of the Active Registers to the Output Registers on a

high to low transition on this pin. This transition will also reset the Active register.

Digital Inputs / Outputs

LRCK - Left/Right Clock, Pin 12.

LRCK determines which channel, left or right, is to be output on SDATA. The relationship

between LRCK, SCLK and SDATA is controlled by DIF0 and DIF1. Although the outputs for

each channel are transmitted at different times, Left/Right pairs represent simultaneously

sampled analog inputs. In Master Mode, LRCK is an output clock whose frequency is equal to

the output sample rate, Fs. In Slave Mode, LRCK is an input clock whose frequency must be

equal to Fs.

SCLK - Serial Data Clock, Pin 8.

Clocks the individual bits of the serial data out from the SDATA pin. The relationship between

LRCK, SCLK and SDATA is controlled by DIF0 and DIF1.

In Master Mode, SCLK is an output clock with a frequency of 64x the output sample rate, Fs.

In Slave Mode, SCLK is an input.

Digital Outputs

SDATA - Serial Data Output, Pin 9.

Two’s complement MSB-first serial data of 20 bits is output on this pin. Included in the serial

data output is the 8-bit Input Signal Level Bits. The data is clocked out via the SCLK clock and

the channel is determined by LRCK. The relationship between LRCK, SCLK and SDATA is

controlled by DIF0 and DIF1.

CS5334 CS5335

DS237PP2

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