DS2751

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POR—POR Indicator bit. This bit is set to a 1 when the DS2751 experiences a power-on-reset (POR)

event. To use the POR bit to detect a power-on-reset, the POR bit must be set to a 0 by the host system

upon power-up and after each subsequent occurrence of a POR.

PIO—PIO Pin Sense and Control. See the Programmable I/O section for details on this read/write bit.

X—Reserved Bits.

1-WIRE BUS SYSTEM

The 1-Wire bus is a system that has a single bus master and one or more slaves. A multidrop bus is a 1-

Wire bus with multiple slaves. A single-drop bus has only one slave device. In all instances, the DS2751

is a slave device. The bus master is typically a microprocessor in the host system. The discussion of this

bus system consists of four topics: 64-Bit Net Address, Hardware Configuration, Transaction Sequence,

and 1-Wire Signaling.

64-BIT NET ADDRESS

Each DS2751 has a unique, factory-programmed 1-Wire net address that is 64 bits in length. The first 8

bits are the 1-Wire family code (51h for DS2751). The next 48 bits are a unique serial number. The last 8

bits are a CRC of the first 56 bits (see Figure 11). The 64-bit net address and the 1-Wire I/O circuitry built

into the device enable the DS2751 to communicate through the 1-Wire protocol detailed in the 1-Wire

Bus System section of this data sheet.

Figure 11. 1-WIRE NET ADDRESS FORMAT

8-Bit CRC

48-Bit Serial Number

8-Bit Family

Code (51h)

MSb

LSb

CRC GENERATION

The DS2751 has an 8-bit CRC stored in the most significant byte of its 1-Wire net address. To ensure

error-free transmission of the address, the host system can compute a CRC value from the first 56 bits of

the address and compare it to the CRC from the DS2751. The host system is responsible for verifying the

CRC value and taking action as a result. The DS2751 does not compare CRC values and does not prevent

a command sequence from proceeding as a result of a CRC mismatch. Proper use of the CRC can result

in a communication channel with a very high level of integrity.

The CRC can be generated by the host using a circuit consisting of a Shift Register and XOR gates as

shown in Figure 12, or it can be generated in software. Additional information about the Dallas 1-Wire

CRC is available in Application Note 27: Understanding and Using Cyclic Redundancy Checks with

Dallas Semiconductor Touch Memory Products.

In the circuit in Figure 12, the shift bits are initialized to 0. Then, starting with the least significant bit of

the family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered, then

the serial number is entered. After the 48th bit of the serial number has been entered, the Shift Register

contains the CRC value.