High Speed CMOS Logic – 54HC20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Die Size (Unsawn)

1200 x 1200

47 x 47

µm

mils

Minimum Bond Pad Size

106 x 106

4 x 4

µm

mils

Die Thickness

350 (±20)

13.78 (±0.79)

µm

mils

Top Metal Composition

Al 1%Si 1.1µm

Back Metal Composition

N/A – Bare Si

Dual 4-Input NAND Gate IC in bare die form

Low Input Current: 1µA

Output Drive Capability: 10 LSTTL loads

Operating Voltage Range: 2V to 6V

CMOS High Noise Immunity

Function compatible with 54LS20

Full Military Temperature Range.

Rev 1.0

7/5/2019

Features:

Ordering Information

The following part suffixes apply:

The 54HC20 Dual 4-Input NAND Gate is made using a

2.5µm 5V CMOS process & combines the high speed

of LSTTL with CMOS low power consumption. The

device performs Boolean functions Y = (A • B • C • D)

or Y = A + B + C + D in positive logic. Inputs accept

standard CMOS outputs or LSTTL outputs using pull-

up resistors. Internal circuitry comprises 3 stages &

includes buffered output for high noise immunity &

stability. Inputs are equipped with protection circuits

against static discharge & transient excess voltage.

Description

Die Dimensions in µm (mils)

1200 (47)

No suffix - MIL-STD-883 /2010B Visual Inspection

“H” - MIL-STD-883 /2010B Visual Inspection

+ MIL-PRF-38534 Class H LAT

“K” - MIL-STD-883 /2010A Visual Inspection (Space)

+ MIL-PRF-38534 Class K LAT

LAT = Lot Acceptance Test.

For further information on LAT process flows see below.

 

 

 

 

 

 

www.siliconsupplies.com\quality\bare-die-lot-qualification

Supply Formats:

Mechanical Specification

Default – Die in Waffle Pack (400 per tray capacity)

Sawn Wafer on Tape – On request

Unsawn Wafer – On request

Die Thickness <> 350µm(14 Mils) – On request

Assembled into Ceramic Package – On request

Page 1 of 5 

www.siliconsupplies.com