High Speed CMOS Logic – 74HC595

8-bit shift registers with 3-state output latches in bare die form

Rev 1.0

05/02/19

Output Drive Capability: 15 LSTTL Loads

Low Input Current: 1µA

Outputs directly interface CMOS, NMOS and TTL

Operating Voltage Range: 2V to 6V

CMOS High Noise Immunity

 

Function compatible with 74LS595.

Features:

Ordering Information

The following part suffixes apply:

The 74HC595 is an 8–bit serial-in to parallel-out shift

register which drives an 8–bit D–type latch with 3–state

outputs. Both register and latch have independent

positive triggered clock inputs. All registers capture

data on rising edge and change output on the falling

edge. If both clocks are connected together the input

shift register is always one clock cycle ahead of the

output register. The shift register also features

asynchronous reset. Device inputs are compatible with

standard CMOS outputs; with pull-up resistors, they are

Description

Die Dimensions in µm (mils)

1030 (41)

Die Size (Unsawn)

1030 x 770

41 x 30

µm

mils

Minimum Bond Pad Size

70 x 70

2.76 x 2.76

µm

mils

Die Thickness

280 (±20)

13.02 (±0.79)

µm

mils

Top Metal Composition

Al-Si-Cu 2.8 µm

Back Metal Composition

N/A – Bare Si

No suffix - MIL-STD-883 /2010B Visual Inspection

“H” - MIL-STD-883 /2010B Visual Inspection

+ MIL-PRF-38534 Class H LAT

“K” - MIL-STD-883 /2010A Visual Inspection (Space)

+ MIL-PRF-38534 Class K LAT

LAT = Lot Acceptance Test.

For further information on LAT process flows see below.

www.siliconsupplies.com\quality\bare-die-lot-qualification

Supply Formats:

Mechanical Specification

Default – Die in Waffle Pack (400 per tray capacity)

Sawn Wafer on Tape – On request

Unsawn Wafer – On request

Die Thickness <> 280µm(11 Mils) – On request

Assembled into Ceramic Package – On request

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