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NM1282KSLAXAL Datasheet(PDF) 32 Page - Nanya Technology Corporation. |
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NM1282KSLAXAL Datasheet(HTML) 32 Page - Nanya Technology Corporation. |
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32 / 120 page ![]() Version 1.3 32 Nanya Technology Corp. 06/2018 All Rights Reserved. © 2Gb SLC NAND + 2Gb LPDDR2 NM1282KSLAXAL NTC Proprietary Level: Property Internal addressing in relation with the Districts To use Multi Page Program operation, the internal addressing should be considered in relation with the District. • The device consists from 2 Districts. • Each District consists from 1024 erase blocks. • The allocation rule is follows. District 0: Block 0, Block 2, Block 4, Block 6,···, Block 2046 District 1: Block 1, Block 3, Block 5, Block 7,···, Block 2047 Address input restriction for the Multi Page Program with Data Cache operation There are following restrictions in using Multi Page Program with Data Cache; (Restriction) Maximum one block should be selected from each District. Same page address (PA0 to PA5) within two districts has to be selected. For example; (80) [District 0, Page Address 0x00000] (11) (81) [District 1, Page Address 0x00040] (15 or 10) (80) [District 0, Page Address 0x00001] (11) (81) [District 1, Page Address 0x00041] (15 or 10) (Acceptance) There is no order limitation of the District for the address input. For example, following operation is accepted; (80) [District 0] (11) (81) [District 1] (15 or 10) (80) [District 1] (11) (81) [District 0] (15 or 10) It requires no mutual address relation between the selected blocks from each District. Operating restriction during the Multi Page Program with Data Cache operation (Restriction) The operation has to be terminated with “10h” command. Once the operation is started, no commands other than the commands shown in the timing diagram is allowed to be input except for Status Read command and reset command. |
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