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VP1310 Datasheet(PDF) 1 Page - Supertex, Inc |
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VP1310 Datasheet(HTML) 1 Page - Supertex, Inc |
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1 / 4 page ![]() 7-251 9 BV DSS /RDS(ON) I D(ON) Order Number / Package BVDGS (max) (min) TO-92 -40V 25 Ω -0.25A VP1304N3 -60V 25 Ω -0.25A VP1306N3 -100V 25 Ω -0.25A VP1310N3 VP1304 VP1306 VP1310 Advanced DMOS Technology These enhancement-mode (normally-off) transistors utilize a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inher- ent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally-induced secondary breakdown. Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Note: See Package Outline section for dimensions. P-Channel Enhancement-Mode Vertical DMOS FETs Package Options Features Free from secondary breakdown Low power drive requirement Ease of paralleling Low CISS and fast switching speeds Excellent thermal stability Integral Source-Drain diode High input impedance and high gain Complementary N- and P-channel devices Applications Motor controls Converters Amplifiers Switches Power supply circuits Drivers (relays, hammers, solenoids, lamps, memories, displays, bipolar transistors, etc.) Absolute Maximum Ratings Drain-to-Source Voltage BVDSS Drain-to-Gate Voltage BVDGS Gate-to-Source Voltage ± 20V Operating and Storage Temperature -55 °C to +150°C Soldering Temperature* 300 °C * Distance of 1.6 mm from case for 10 seconds. Ordering Information TO-92 S G D |
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