SC16C554DB datasheet(32/51 Pages) PHILIPS

32 / 51 page

9397 750 13133

Product data sheet

Rev. 01 — 9 February 2005

32 of 51

Philips Semiconductors

SC16C554B/554DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs

7.8 Modem Status Register (MSR)

This register provides the current state of the control interface signals from the modem, or

other peripheral device to which the SC16C554B/554DB is connected. Four bits of this

whenever a control input from the modem changes state. These bits are set to a logic 0

whenever the CPU reads this register.

LSR[0]

Receive data ready.

Logic 0 = No data in receive holding register or FIFO (normal default

condition).

Logic 1 = Data has been received and is saved in the receive holding

Table 20:

Line Status Register bits description …continued

Bit

Symbol

Description

Table 21:

Modem Status Register bits description

Bit

Symbol

Description

MSR[7]

CD (active HIGH, logical 1). Normally this bit is the complement of the CD

input. In the loop-back mode this bit is equivalent to the OP2 bit in the MCR

MSR[6]

RI (active HIGH, logical 1). Normally this bit is the complement of the RI

input. In the loop-back mode this bit is equivalent to the OP1 bit in the MCR

MSR[5]

DSR (active HIGH, logical 1). Normally this bit is the complement of the DSR

input. In loop-back mode this bit is equivalent to the DTR bit in the MCR

MSR[4]

CTS (active HIGH, logical 1). CTS functions as hardware ﬂow control signal

input if it is enabled via MCR[5]. Flow control (when enabled) allows starting

and stopping the transmissions based on the external modem CTS signal. A

logic 1 at the CTS pin will stop SC16C554B/554DB transmissions as soon

as current character has ﬁnished transmission. Normally MSR[4] is the

complement of the CTS input. However, in the loop-back mode, this bit is

equivalent to the RTS bit in the MCR register.

MSR[3]

∆CD [1]

Logic 0 = No CD change (normal default condition).

Logic 1 = The CD input to the SC16C554B/554DB has changed state

since the last time it was read. A modem Status Interrupt will be

generated.

MSR[2]

∆RI [1]

Logic 0 = No RI change (normal default condition).

Logic 1 = The RI input to the SC16C554B/554DB has changed from a

logic 0 to a logic 1. A modem Status Interrupt will be generated.

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