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LTC1709-7

The secondary output voltage VSEC is normally set as

shown in Figure 5a by the turns ratio N of the transformer:

VSEC ≅ (N + 1) VOUT

However, if the controller goes into Burst Mode operation

and halts switching due to a light primary load current,

then VSEC will droop. An external resistive divider from

VSEC to the FCB pin sets a minimum voltage VSEC(MIN):

SEC MIN

()

≈+









where R5 and R6 are shown in the Functional Diagram.

If VSEC drops below this level, the FCB voltage forces

temporary continuous switching operation until VSEC is

again above its minimum.

In order to prevent erratic operation if no external connec-

tions are made to the FCB pin, the FCB pin has a 0.18

µA

internal current source pulling the pin high. Include this

current when choosing resistor values R5 and R6.

The following table summarizes the possible states avail-

able on the FCB pin:

Table 2

FCB Pin

Condition

0V to 0.75V

Forced Continuous (Current Reversal

Allowed—Burst Inhibited)

0.85V < VFCB < 4.3V

Minimum Peak Current Induces

Burst Mode Operation

No Current Reversal Allowed

Feedback Resistors

Regulating a Secondary Winding

>4.8V

Burst Mode Operation Disabled

Constant Frequency Mode Enabled

No Current Reversal Allowed

No Minimum Peak Current

Voltage Positioning

Voltage positioning can be used to minimize peak-to-peak

output voltage excursion under worst-case transient load-

ing conditions. The open-loop DC gain of the control loop

is reduced depending upon the maximum load step speci-

fications. Voltage positioning can easily be added to the

LTC1709-7 by loading the ITH pin with a resistive divider

having a Thevenin equivalent voltage source equal to the

APPLICATIO S I FOR ATIO

Figure 8. Active Voltage Positioning Applied to the LTC1709-7

ITH

RT1

INTVCC

17097 F08

LTC1709-7

RT2

midpoint operating voltage of the error amplifier, or 1.2V

(see Figure 8).

The resistive load reduces the DC loop gain while main-

taining the linear control range of the error amplifier. The

worst-case peak-to-peak output voltage deviation due to

transient loading can theoretically be reduced to half or

alternatively the amount of output capacitance can be

reduced for a particular application. A complete explana-

tion is included in Design Solutions 10 or the LTC1736

data sheet. (See www.linear-tech.com)

Efficiency Considerations

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can be

expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percentage

of input power.

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

losses in LTC1709-7 circuits: 1) I2R losses, 2) Topside

MOSFET transition losses, 3) INTVCC regulator current

and 4) LTC1709-7 VIN current (including loading on the

differential amplifier output).

1) I2R losses are predicted from the DC resistances of the

fuse (if used), MOSFET, inductor, current sense resistor,

and input and output capacitor ESR. In continuous mode

the average output current flows through L and RSENSE,

but is “chopped” between the topside MOSFET and the

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