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CY2287
3
Function Table
SEL2[2]
SEL1
SEL0
CPU
(MHz)
SDRAM
(MHz)
3V66
(MHz)
PCI
(MHz)
USB
(MHz)
REF
(MHz)
APIC[4]
(MHz)
APIC[5]
(MHz)
0
0
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0
0
1
TCLK[3]/2
TCLK/2
TCLK/3
TCLK/8
TCLK/2
TCLK
TCLK/16
TCLK/8
0
1
0
66.67
100
66.67
33.33
48
14.318
16.67
33.33
0
1
1
100
100
66.67
33.33
48
14.318
16.67
33.33
1
0
0
66.67
100
66.67
33.33
48
14.318
16.67
33.33
1
0
1
100
100
66.67
33.33
48
14.318
16.67
33.33
1
1
0
66.67
100
66.67
33.33
48
14.318
16.67
33.33
1
1
1
100
100
66.67
33.33
48
14.318
16.67
33.33
Spread Spectrum[2]
SEL2[2]
SEL1
SEL0
Spread Spectrum Margin
X
000
N/A
X
001
N/A
0
XXX
N/A
1
010
–0.6%
1
011
–0.6%
1
100
–0.25%
1
101
–0.25%
1
110
–0.4%
1
111
–0.4%
Actual Clock Frequency Values
Clock Output
Target
Frequency (MHz)
Actual
Frequency (MHz)
PPM
CPUCLK
66.67
66.288
–5230
CPUCLK
100.0
99.432
–5680
USBCLK
48.0
48.008
+167
Notes:
2.
Not a dedicated input pin. This selection must be addressed via I2C interface.
3.
TCLK supplied on the XTALIN pin in Test Mode.
4.
SEL33 = LOW (power-on latch input).
5.
SEL33 = HIGH (power-on latch input).
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