MSP430F155IPM datasheet(39/70 Pages) TI

39 / 70 page

MSP430x15x, MSP430x16x, MSP430x161x

MIXED SIGNAL MICROCONTROLLER

SLAS368D− OCTOBER 2002− REVISED MARCH 2005

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)

12-bit ADC, built-in reference

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

Positive built-in reference

REF2_5V = 1 for 2.5 V

IVREF+max ≤ IVREF+≤ IVREF+min

3 V

2.4

2.5

2.6

VREF+

Positive built-in reference

voltage output

REF2_5V = 0 for 1.5 V

IVREF+max ≤ IVREF+≤ IVREF+min

2.2 V/3 V

1.44

1.5

1.56

REF2_5V = 0, IVREF+max ≤ IVREF+≤ IVREF+min

2.2

AVCC(min)

AVCC minimum voltage,

Positive built-in reference

REF2_5V = 1, −0.5mA

≤ IVREF+≤ IVREF+min

2.8

AVCC(min)

Positive built-in reference

active

REF2_5V = 1, −1mA

≤ IVREF+≤ IVREF+min

2.9

Load current out of VREF+

2.2 V

0.01

−0.5

IVREF+

Load current out of VREF+

terminal

3 V

0.01

−1

IVREF+ = 500 µA +/− 100 µA

2.2 V

±2

Load-current regulation

Analog input voltage ~0.75 V;

REF2_5V = 0

3 V

±2

LSB

IL(VREF)+ †

Load-current regulation

VREF+ terminal

IVREF+ = 500 µA ± 100 µA

Analog input voltage ~1.25 V;

REF2_5V = 1

3 V

±2

LSB

Load current regulation

IVREF+ =100 µA → 900 µA,

IDL(VREF) +‡

Load current regulation

VREF+ terminal

CVREF+=5 µF, ax ~0.5 x VREF+

Error of conversion result

≤ 1 LSB

3 V

CVREF+

Capacitance at pin VREF+

(see Note 1)

REFON =1,

0 mA

≤ IVREF+ ≤ IVREF+max

2.2 V/3 V

µF

TREF+†

Temperature coefficient of

built-in reference

IVREF+ is a constant in the range of

0 mA

≤ IVREF+ ≤ 1 mA

2.2 V/3 V

±100 ppm/°C

tREFON†

Settle time of internal

reference voltage (see

Figure 16 and Note 2)

IVREF+ = 0.5 mA, CVREF+ = 10 µF,

VREF+ = 1.5 V, VAVCC = 2.2 V

† Not production tested, limits characterized

‡ Not production tested, limits verified by design

NOTES:

1. The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses

two capacitors between pins VREF+ and AVSS and VREF−/VeREF− and AVSS: 10 µF tantalum and 100 nF ceramic.

2. The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external

capacitive load.

CVREF+

µF

1 ms

10 ms

100 ms

tREFON

tREFON ≈ .66 x CVREF+ [ms] with CVREF+ in µF

100

µF

Figure 16. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+

MSP430F155IPM Datasheet(PDF) 39 Page - Texas Instruments

MSP430F155IPM Datasheet(HTML) 39 Page - Texas Instruments

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