T25D64AFIPR datasheet(39/74 Pages) HMSEMI

39 / 74 page

7.1 Configuration and Status Commands

7.1.1 Read Status Register (05h/35h/15h)

The Read Status Register commands allow the 8-bit Status Registers to be read. The command is

entered by driving CS# low and shifting the instruction code “05h” for Status Register-1, “35h” for Status

then shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in

Figure 7.1. The Status Register bits are shown in Section 6.2, Status Registers.

The Read Status Register-1 (05h) command may be used at any time, even during a Program, Erase, or

Write Status Registers cycle. This allows the BUSY status bit to be checked to determine when the operation

is complete and if the device can accept another command.

Figure 7.1a Read Status Register Instruction(SPI Mode)

Figure 7.1b Read Status Register Instruction(QPI Mode)

7.1.2 Write Enable (06h)

The Write Enable instruction (Figure 7.2) sets the Write Enable Latch (WEL) bit in the Status Register to

a 1. The WEL bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase and Write

Status Register instruction. The Write Enable instruction is entered by driving CS# low, shifting the instruction

code “06h” into the Data Input (DI) pin on the rising edge of CLK, and then driving CS# high.

HM25Q128A

T25D64AFIPR Datasheet(PDF) 39 Page - Shenzhen Huazhimei Semiconductor Co., Ltd