T25S16AFEPR datasheet(57/74 Pages) HMSEMI

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Figure 7.30a Read Manufacturer/Device ID(SPI Mode)

Figure 7.30b Read Manufacturer/Device ID(QPI Mode)

7.5.4 Read Identification (RDID) (9Fh)

For compatibility reasons, the

HM25Q128A provides several instructions to electronically determine the

identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI

compatible serial memories that was adopted in 2003.

The instruction is initiated by driving the CS# pin low and shifting the instruction code “9Fh”. The JEDEC

assigned Manufacturer ID byte and two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are

then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 7.31. For

memory type and capacity values, refer to Manufacturer and Device Identification table.

Figure 7.31a Read JEDEC ID(SPI Mode)

Figure 7.31b Read JEDEC ID(QPI Mode)

7.5.5 Read SFDP Register (5Ah)

The Read SFDP command is initiated by driving the CS# pin low and shifting the instruction code “5Ah”

followed by a 24-bit address (A23-A0) into the DI pin. Eight “dummy” clocks are also required before the

SFDP register contents are shifted out on the falling edge of the 40th CLK with most significant bit (MSB) first

as shown in Figure 7.32.

HM25Q128A

T25S16AFEPR Datasheet(PDF) 57 Page - Shenzhen Huazhimei Semiconductor Co., Ltd