IXFN38N100P

IXYS Reserves the Right to Change Limits, Test Conditions, and Dimensions.

Fig. 7. Input Admittance

0

10

20

30

40

50

60

5.5

6.0

6.5

7.0

7.5

8.0

8.5

9.0

9.5

10.0

25

- 40

Fig. 8. Transconductance

0

5

10

15

20

25

30

35

40

45

50

55

60

0

1020

3040

50

60

7080

125

25

Fig. 9. Forward Voltage Drop of Intrinsic Diode

0

20

40

60

80

100

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

Fig. 10. Gate Charge

0

2

4

6

8

10

12

14

16

0

50

100

150

200

250

300

350

400

450

500

Fig. 11. Capacitance

10

100

1,000

10,000

100,000

0

5

10

15

20

25

30

35

40

f = 1 MHz

Ciss

Crss

Coss

Fig. 12. Forward-Bias Safe Operating Area

0.1

1

10

100

1000

10

100

1,000

Single Pulse

1ms

100μs

10ms

DC

100ms

25μs