AM186EM-33VCSLASHW datasheet(35/98 Pages) AMD

35 / 98 page

Am186/188EM and Am186/188EMLV Microcontrollers

P R E L IMINAR Y

BUS OPERATION

The industry-standard 80C186 and 80C188 microcon-

trollers use a multiplexed address and data (AD) bus.

The address is present on the AD bus only during the

t1 clock phase. The Am186EM and Am188EM microcon-

trollers continue to provide the multiplexed AD bus and, in

addition, provide a nonmultiplexed address (A) bus. The A

bus provides an address to the system for the complete

bus cycle (t1–t4).

For systems where power consumption is a concern, it

is possible to disable the address from being driven on

the AD bus on the Am186EM microcontroller and on

the AD and AO buses on the Am188EM microcontroller

during the normal address portion of the bus cycle for

accesses to UCS and/or LCS address spaces. In this

mode, the affected bus is placed in a high impedance

state during the address portion of the bus cycle. This

feature is enabled through the DA bits in the UMCS and

LMCS registers. When address disable is in effect, the

number of signals that assert on the bus during all nor-

mal bus cycles to the associated address space is re-

duced, decreasing power consumption and reducing

processor switching noise. On the Am188EM micro-

controller, the address is driven on A015–A08 during

the data portion of the bus cycle, regardless of the set-

ting of the DA bits.

If the ADEN pin is pulled Low during processor reset, the

value of the DA bits in the UMCS and LMCS registers is

ignored and the address is driven on the AD bus for all ac-

cesses, thus preserving the industry-standard 80C186

and 80C188 microcontrollers’ multiplexed address bus

and providing support for existing emulation tools.

The following diagrams show the Am186EM and

Am188EM microcontroller bus cycles when the ad-

dress bus disable feature is in effect.

Figure 3 shows the affected signals during a normal

read or write operation for an Am186EM microcontrol-

ler. The address and data will be multiplexed onto the

AD bus.

Figure 4 shows an Am186EM microcontroller bus cycle

when address bus disable is in effect. This results in

having the AD bus operate in a nonmultiplexed ad-

dress/data mode. The A bus will have the address dur-

ing a read or write operation.

Figure 5 shows the affected signals during a normal

read or write operation for an Am188EM microcontrol-

ler. The multiplexed address/data mode is compatible

with the 80C186 and 80C188 microcontrollers and

might be used to take advantage of existing logic or pe-

ripherals.

Figure 6 shows an Am188EM microcontroller bus cycle

when address bus disable is in effect. The address and

data is not multiplexed. The AD7–AD0 signals will have

only data on the bus, while the AO bus will have the ad-

dress during a read or write operation.

Figure 3.

Am186EM Microcontroller Address Bus—Normal Read and Write Operation

CLKOUTA

AD15–AD0

(Read)

Data

AD15–AD0

(Write)

LCS or UCS

Address

Data

Address

Phase

Data

Phase

A19–A0

Address

MCSx, PCSx

AM186EM-33VC/W Datasheet(PDF) 35 Page - Advanced Micro Devices

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