RTL8100B(L)
2001-11-9
Rev.1.41
39
BIST: Built-in Self Test
Reads will return a 0, writes are ignored.
IOAR: This register specifies the BASE IO address which is required to build an address map during configuration. It also
specifies the number of bytes required as well as an indication that it can be mapped into IO space.
Bit
Symbol
Description
31-8
IOAR31-8 BASE IO Address: This is set by software to the Base IO address for the operational register map.
7-2
IOSIZE
Size Indication: Read back as 0. This allows the PCI bridge to determine that the RTL8100B(L)
requires 256 bytes of IO space.
1
-
Reserved
0
IOIN
IO Space Indicator: Read only. Set to 1 by the RTL8100B(L) to indicate that it is capable of being
mapped into IO space.
MEMAR: This register specifies the base memory address for memory accesses to the RTL8100B(L) operational registers. This
register must be initialized prior to accessing any of the RTL8100B(L)'s register with memory access.
Bit
Symbol
Description
31-8
MEM31-8 Base Memory Address: This is set by software to the base address for the operational register map.
7-4
MEMSIZE Memory Size: These bits return 0, which indicates that the RTL8100B(L) requires 256 bytes of
Memory Space.
3
MEMPF
Memory Prefetchable: Read only. Set to 0 by the RTL8100B(L).
2-1
MEMLOC Memory Location Select: Read only. Set to 0 by the RTL8100B(L). This indicates that the base
register is 32-bit wide and can be placed anywhere in the 32-bit memory space.
0
MEMIN
Memory Space Indicator: Read only. Set to 0 by the RTL8100B(L) to indicate that it is capable of
being mapped into memory space.
SVID: Subsystem Vendor ID. This field will be set to a value corresponding to PCI Subsystem Vendor ID in the external
EEPROM. If there is no EEPROM, this field will default to a value of 10ECh which is Realtek Semiconductor's PCI
Subsystem Vendor ID.
SMID: Subsystem ID. This field will be set to value corresponding to PCI Subsystem ID in the external EEPROM. If there is no
EEPROM, this field will default to a value of 8139h.
BMAR: This register is disabled in the RTL8100B(L).
ILR: Interrupt Line Register
The Interrupt Line Register is an 8-bit register used to communicate with the routing of the interrupt. It is written by the
POST software to set interrupt line for the RTL8100B(L).
IPR: Interrupt Pin Register
The Interrupt Pin register is an 8-bit register indicating the interrupt pin used by the RTL8100B(L). The RTL8100B(L)
uses INTA interrupt pin. Read only. IPR = 01H.
MNGNT: Minimum Grant Timer: Read only
Specifies how long a burst period the RTL8100B(L) needs at 33 MHz clock rate in units of 1/4 microsecond. This field will
be set to a value from the external EEPROM. If there is no EEPROM, this field will default to a value of 20h.
MXLAT: Maximum Latency Timer: Read only
Specifies how often the RTL8100B(L) needs to gain access to the PCI bus in units of 1/4 microseconds. This field will be
set to a value from the external EEPROM. If there is no EEPROM, this field will default to a value of 20h.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
