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CY28317-2
Document #: 38-07094 Rev. *B
Page 18 of 21
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
24.004
MHz
fD
Deviation from 24 MHz
(24.004 – 24)/24
+167
ppm
m/n
PLL Ratio
(14.31818 MHz x 57/34 = 24.004 MHz)
57/34
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
2
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
2
V/ns
tD
Duty Cycle
Measured on the rising and falling edges at 1.5V
45
55
%
fST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to fre-
quency stabilization.
3ms
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
40
Ω
Ordering Information
Ordering Code
Package Type
Operating Range
CY28317PVC-2
48-pin SSOP
Commercial, 0°C to 70°C
CY28317PVC-2T
48-pin SSOP - Tape and Reel
Commercial, 0°C to 70°C
CY28317ZC-2
48-pin TSSOP
Commercial, 0°C to 70°C
CY28317ZC-2T
48-pin TSSOP - Tape and Reel
Commercial, 0°C to 70°C
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