SWITCHING LOSS

The next loss is the switching loss that is caused by the need

to charge and discharge the gate capacitance of the FETs

every cycle. This can be approximated by:

P

for the PMOS, and the same approach can be adapted for

the NMOS:

P

TRANSITIONAL LOSS

The last FET power loss is the transitional loss. This is

caused by switching the PMOS while it is conducting current.

This approach only models the PMOS transition, the NMOS

loss is considered negligible because it has minimal drain to

source voltage when it switches due to the conduction of the

body diode. Therefore the transitional loss of the PMOS can

be modeled by:

P

t

found in their corresponding datasheet. Typically these num-

bers are simulated using a 6

Ω drive, which corresponds well

to the LM1770. Given this, no adjustment is needed.

DCR LOSS

The last source of power loss in the system that needs to be

calculated is the loss associated with the inductor resistance

(DCR) which can be calculated by

P

2

EFFICIENCY

The efficiency,

η, can then be calculated by summing all the

power losses and then using the equation below:

Thermals

By breaking down the individual power loss in each compo-

nent it makes it easy to determine the temperature rise of

each component. Generally the expected temperature rise

of the LM1770 is extremely low as it is not in the power path.

Therefore the only two items of concern are the PMOS and

the NMOS. The power loss in the PMOS is the sum of the

conduction loss and transitional loss, while the NMOS only

has conduction loss. It is assumed that any loss associated

with the body diode conduction during the dead-time is

negligible.

For completeness of design it is important to watch out for

the temperature rise of the inductor. Assuming the inductor is

kept out of saturation the predominant loss will be the DC

copper resistance. At higher frequencies, depending on the

core material, the core loss could approach or exceed the

DCR losses. Consult with the inductor manufacturer for ap-

propriate temp curves based on current.

Layout

The LM1770, like all switching regulators, requires careful

attention to layout to ensure optimal performance. The fol-

lowing steps should be taken to aid in the layout. For more

information refer to Application Note AN-1299.

1.

Ensure that the ground connections of the input capaci-

tor, output capacitor and NMOS are as close as pos-

sible. Ideally these should all be grounded together in

close proximity on the component side of the board.

2.

Keep the switch node small to minimize EMI without

degrading thermal cooling of the FETs.

3.

Locate the feedback resistors close to the IC and keep

the feedback trace as short as possible. Do not run any

feedback traces near the switch node.

4.

Keep the gate traces short and keep them away from the

switch node as much as possible.

5.

If a small bypass capacitor is used on V

it as close to the pin, with the ground connection as

close to the chip ground as possible.

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