CP3SP33 datasheet(2/6 Pages) NSC

2 / 6 page

www.national.com

2.0

Features

CPU Features

Fully static RISC processor core, capable of operating

from 0 to 96 MHz with zero wait/hold state

Minimum 10.4 ns instruction cycle time with a 96-MHz in-

ternal clock frequency, based on a 12-MHz external input

4K-byte, 4-way set-associative instruction cache

69 independently vectored peripheral interrupts

DSP Features

Capable of operating up to 96 MHz

16-bit fixed-point arithmetic, dual-MAC architecture

32-bit interface to 4K-byte RAM shared with CPU

32-bit external bus interface

Bus master interface to audio peripherals and I/O

Memory

4K bytes CPU instruction cache

32K bytes CPU data RAM

4K bytes CPU/DSP shared RAM

24K bytes DSP program RAM

24K bytes DSP data RAM

8K bytes Bluetooth sequencer and data RAM

Addresses up to 32M bytes of external memory

Broad Range of Hardware Communications Peripher-

als

Bluetooth Lower Link Controller (LLC) including a shared

7K byte Bluetooth data RAM and 1K byte Bluetooth Se-

quencer RAM

Universal Serial Bus (USB) 2.0 On-The-Go

Audio/telematics codec with dual ADC inputs and high-

quality stereo DAC output

Two CAN interfaces with 15 message buffers conforming

to CAN specification 2.0B active

Two ACCESS.bus serial bus interfaces (I2C compatible)

Two 8/16-bit SPI, Microwire/Plus serial interfaces

I2S digital audio bus interface

Four Universal Asynchronous Receiver/Transmitter

(UART) channels, one channel has USART capability

Advanced Audio Interface (AAI) to connect to external 8/

13-bit PCM Codecs as well as to ISDN-Controllers

through the IOM-2 interface (slave only)

Two CVSD/PCM converters, for supporting two bidirec-

tional audio connections

External Bus Interface Shared Between CPU and DSP

16/32-bit data bus

23-bit address bus

3 programmable chip select outputs

Up to 32M bytes external memory

8-level write buffer

General-Purpose Hardware Peripherals

10-channel, 10-bit A/D Converter (ADC)

16-channel DMA controller

Dual 16-bit Multi-Function Timer (MFT)

Dual Versatile Timer Units (VTU), each with four inde-

pendent timers

Timing and Watchdog Unit

Extensive Power and Clock Management Support

Two Phase Locked Loops (PLL) for synthesizing inde-

pendent system and audio peripheral clocks

Two independent oscillators for Active mode (12 MHz)

and Power Save mode (32.768 kHz) clocks

Low-power modes (Power Save, Idle, and Halt) for slow-

ing or stopping clocks to optimize power consumption

while meeting application needs

Flexible I/O

Up to 64 general-purpose I/O pins (shared with on-chip

peripheral I/O)

Programmable I/O pin characteristics: TRI-STATE out-

put, push-pull output, weak pullup/pulldown input, high-

impedance input, high-speed drive capability

Schmitt triggers on general-purpose inputs

Multi-Input Wake-Up (MIWU) capability

Power Supply

I/O port operation at 3.0–3.3V

Core logic operation at 1.8V

On-chip power-on reset

Temperature Range

-40°C to +85°C (Industrial)

Packages

FBGA-224, FBGA-144

Complete Development Environment

Pre-integrated hardware and software support for rapid

prototyping and production

Multi-file C source editor, source debugger, and project

manager

Comprehensive, integrated, one-stop technical support

Bluetooth Protocol Stack

Applications can interface to the high-level protocols or

directly to the low-level Host Controller Interface (HCI)

Transport layer support allows HCI command-based in-

terface over UART port

Baseband (Link Controller) hardware minimizes the

bandwidth demand on the CPU

Link Manager (LM)

Logical Link Control and Adaptation Protocol (L2CAP)

Service Discovery Protocol (SDP)

RFCOMM Serial Port Emulation Protocol

All packet types, piconet, and scatternet functionality

CP3SP33 Connectivity Processor Selection Guide

NSID

Speed

(MHz)

Temp. Range

I/Os

Package

Type

CP3SP33SMS

-40° to +85°C

FBGA-224

CP3SP33SMR

-40° to +85°C

FBGA-144

CP3SP33 Datasheet(PDF) 2 Page - National Semiconductor (TI)

CP3SP33 Datasheet(HTML) 2 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6

Datasheet Download

Link URL