NMOS linear image sensor

S3901/S3904 series

0.3

0.2

0.1

0

200

400

600

800

1000

1200

WAVELENGTH (nm)

(Ta=25 ˚C)

Terminal

Input or output

Description

φ1, φ2

Input

(CMOS logic compatible)

Pulses for operating the MOS shift register. The video data rate is

equal to the clock pulse frequency since the video output signal is

obtained synchronously with the rise of φ2 pulse.

φst

Input

(CMOS logic compatible)

Pulse for starting the MOS shift register operation. The time interval

between start pulses is equal to the signal accumulation time.

Vss

-

Connected to the anode of each photodiode. This should be

grounded.

Vscg

Input

Used for restricting blooming. This should be grounded.

Vscd

Input

Used for restricting blooming. This should be biased at a voltage

equal to the video bias voltage.

Active video

Output

Video output signal. Connects to photodiode cathodes when the

address is on. A positive voltage should be applied to the video

line in order to use photodiodes with a reverse voltage. When the

amplitude of φ1 and φ2 is 5 V, a video bias voltage of 2 V is

recommended.

Dummy video

Output

This has the same structure as the active video, but is not

connected to photodiodes, so only spike noise is output. This

should be biased at a voltage equal to the active video or left as an

open-circuit when not needed.

Vsub

-

Connected to the silicon substrate. This should be grounded.

End of scan

Output

(CMOS logic compatible)

This should be pulled up at 5 V by using a 10 kΩ resistor. This is a

negative going pulse that appears synchronously with the φ2

timing right after the last photodiode is addressed.

NC

-

Should be grounded.

(Typ. Vb=2 V, V =5 V, light source: 2856 K)

10

–5

10

2

10

1

10

0

10

–1

10

–2

10

–3

10

–4

10

–3

10

–2

10

–1

10

0

EXPOSURE (lx · s)

S3904 SERIES

SATURATION EXPOSURE

S3901 SERIES

SATURATION

CHARGE

KMPDB0149EA

Figure 5 Spectral response (typical example)

Figure 6 Output charge vs. exposure

KMPDB0042EB

s Construction of image sensor

The NMOS image sensor consists of a scanning circuit made

up of MOS transistors, a photodiode array, and a switching

transistor array that addresses each photodiode, all integrated

onto a monolithic silicon chip. Figure 1 shows the circuit of a

NMOS linear image sensor.

The MOS scanning circuit operates at low power consump-

tion and generates a scanning pulse train by using a start

pulse and 2-phase clock pulses in order to turn on each ad-

dress sequentially. Each address switch is comprised of an

NMOS transistor using the photodiode as the source, the

video line as the drain and the scanning pulse input section

as the gate.

The photodiode array operates in charge integration mode

so that the output is proportional to the amount of light expo-

sure (light intensity × integration time).

Each cell consists of an active photodiode and a dummy

photodiode, which are respectively connected to the active

video line and the dummy video line via a switching transis-

tor. Each of the active photodiodes is also connected to the

saturation control drain via the saturation control transistor,

so that the photodiode blooming can be suppressed by

grounding the saturation control gate. Applying a pulse sig-

nal to the saturation control gate triggers all reset. (See “Aux-

iliary functions”.)

Figure 2 shows the schematic diagram of the photodiode

active area. This active area has a PN junction consisting of

an N-type diffusion layer formed on a P-type silicon substrate.

A signal charge generated by light input accumulates as a

capacitive charge in this PN junction. The N-type diffusion

layer provides high UV sensitivity but low dark current.