74LVC1G125 datasheet(5/8 Pages) SS

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Low Voltage CMOS Logic – 74LVC1G125

Rev 1.0

29/06/19

AC Electrical Characteristics6

LIMITS

PARAMETER

SYMBOL

VCC

CONDITIONS

25°C

85°C

FULL RANGE

UNITS

1.65 - 1.95V

CL = 30pF,

Input

tr = tf ≤ 2ns,

RL = 1kΩ,

VIN = VCC

2.3 - 2.7V

CL = 30pF,

Input

tr = tf ≤ 2ns,

RL = 500Ω,

VIN = VCC

5.5

2.7V

CL = 50pF,

Input

tr = tf ≤ 2.5ns,

RL = 500Ω,

VIN = 2.7V

5.5

3.0 - 3.6V

CL = 50pF,

Input

tr = tf ≤ 2.5ns,

RL = 500Ω,

VIN = 2.7V

4.5

Propagation

Delay

Input A to

Output Y

(Figure 1,3)

tPLH / tPHL

4.5 - 5.5V

CL = 50pF,

Input

tr = tf ≤ 2.5ns,

RL = 500Ω,

VIN = VCC

4.0

6. Not production tested in die form, characterized by chip design and tested in package

DC Electrical Characteristics Continued (Voltages Referenced to GND)

LIMITS

PARAMETER

SYMBOL

VCC

CONDITIONS

25°C

85°C

FULL RANGE

UNITS

Power-Off

Leakage

Current

IOFF

VIN or VOUT

= 5.5V

±2

µA

Supply

Current

ICC

1.65 -5.5V

VIN = 5.5V

or GND,

IOUT = 0A

µA

Additional

Supply

Current

ΔICC

2.3 - 5.5V

VIN = VCC -

0.6V, IOUT =0A,

Per pad

500

µA

TYPICAL

Input

Capacitance

CIN

3.3V

VIN = GND to

VCC, TJ = 25°C

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