UTC7106

CMOS IC

9

QW-R502-018,B

segments are driven at the same frequency and amplitude and are in phase with BP when OFF, but out of phase

when ON. In all cases negligible DC voltage exists across the segments.

LCD PHASE DRIVER

7

SEGMENT

DECODE

7

SEGMENT

DECODE

7

SEGMENT

DECODE

LATCH

1000 s

COUNTER

,

100 s

COUNTER

,

10 s

COUNTER

,

1 s

COUNTER

,

BACKPLANE

LOGIC

CONTROL

FROM COMPARATOR OUTPUT

CLOCK

40

39

38

OSC 1

OSC 2

OSC 3

FIGURE 5. DIGITAL SECTION

26

37

6.2V

500Ω

TEST

V-

V+

1

21

TYPICAL SEGMENT OUTPUT

SEGMENT

OUTPUT

2mA

0.5mA

V+

INTERNAL DIGITAL GROUND

INTERNAL

DIGITAL

GROUND

*

a

b

a

b

g

f

e

c

d

a

b

g

f

e

c

d

a

b

g

f

e

c

d

TO SWITCH DRIVERS

SYSTEM TIMING

Figure 6 shows the clocking arrangement used in the UTC 7106. Two basic clocking arrangements can be used:

1. Figure 6A. An external oscillator connected to pin 40.

2. Figure 6B. An R-C oscillator using all three pins.

The oscillator frequency is divided by four before it clocks the decade counters. It is then further divided to form

the three convert-cycle phases. These are signal integrate (1000 counts), reference de-integrate(0 to 2000 counts)

and auto-zero(1000 ~ 3000 counts). For signals less than full scale. auto-zero gets the unused portion of reference

de-integrate. This makes a complete measure cycle of 4,000 counts (16,000 clock pulses) independent of input

voltage. For three readings/second, an oscillator frequency of 48kHz would be used.

To achieve maximum rejection of 60Hz pickup, the signal integrate cycle should be a multiple of 60Hz. Oscillator

frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz, 40kHz, 33 1/3kHz, etc should be selected. For 50Hz

rejection, Oscillator frequencies of 200kHz, 100kHz, 66 2/3kHz, 50kHz, 40kHz, etc would be suitable. Note that

40kHz (2.5 readings/second) will reject both 50Hz and 60Hz (also 400Hz and 440Hz).