C9835
Document #: 38-07303 Rev. **
Page 13 of 18
Notes:
32. The time specified is measured from when all VDD’s reach their respective supply rail (3.3V and 2.5V) till the frequency output is stable and operating within the
specifications.
33. Measured from when both SEL1 and SEL0 are switched to low (disable).
34. Device designed for Typical Duty Cycle of 50%.
TLOW
PCI(_F, 1:6) low time[31]
12.0
12.0
12.0
ns
Tr / Tf
PCI(_F, 1:6) rise and fall times[27]
0.5
2.0
0.5
2.0
0.5
2.0
ns
TSKEW
(Any PCI) to (Any PCI) Skew[26,29]
500
500
500
ps
TCCJ
PCI(_F, 1:6) Cycle to Cycle Jitter[26,29]
500
500
500
ps
DOT and USB
TPeriod
DOT and USB (48M[0,1]) period
(conforms to +167 ppm max) [25,26]
20.8299 20.8333 20.8299 20.8333
20.829
20.833
ns
Tr / Tf
DOT and USB rise and fall times[27]
1.0
4.0
1.0
4.0
1.0
4.0
ns
TCCJ
DOT and USB Cycle to Cycle Jitter[26,29]
500
500
500
ps
TCCJ
VCH_CLK Cycle to Cycle Jitter[26]
250
250
250
ps
REF
TPeriod
REF period[25,26]
69.8413
71.0
69.8413
71.0
69.8413
71.0
ns
Tr / Tf
REF rise and fall times[27]
1.0
4.0
1.0
4.0
1.0
4.0
ns
TCCJ
REF Cycle to Cycle Jitter[26]
1000
1000
1000
ps
tpZL, tpZH
Output enable delay (all outputs)[28]
1.0
10.0
1.0
10.0
1.0
10.0
ns
tpLZ, tpHZ
Output disable delay (all outputs)[33]
1.0
10.0
1.0
10.0
1.0
10.0
ns
tstable
All clock stabilization from power-up[32]
333
ms
Tduty
Duty cycle for all outputs[34]
45
55
45
55
45
55
%
AC Parameters (continued)
Parameter
Description
133 MHz Host
100 MHz Host
66 MHz Host
Units
Min.
Max.
Min.
Max.
Min.
Max.
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