HD64F2145 datasheet(401/829 Pages) RENESAS

401 / 829 page

Rev. 2.0, 08/02, page 361 of 788

15.4.4

SCI Initialization (Asynchronous Mode)

Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then

initialize the SCI as shown in figure 15.5. When the operating mode, transfer format, etc., is

changed, the TE and RE bits must be cleared to 0 before making the change using the following

procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is set to 1. Note that clearing

the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and ORER flags in SSR,

or the contents of RDR. When an external clock is used in asynchronous mode, the clock must be

supplied even during initialization.

Wait

Start initialization

Set data transfer/receive format in

SMR and SCMR

[1]

Set CKE1 and CKE0 bits in SCR

(TE and RE bits are 0)

Yes

Set value in BRR

Clear TE and RE bits in SCR to 0

[2]

[3]

Set TE and RE bits in

SCR to 1, and set RIE, TIE, TEIE,

and MPIE bits

[4]

1-bit interval elapsed?

[1] Set the clock selection in SCR.

Be sure to clear bits RIE, TIE,

TEIE, and MPIE, and bits TE and

RE, to 0.

When the clock is selected in

asynchronous mode, it is output

immediately after SCR settings are

made.

[2] Set the data transfer/receive format

in SMR and SCMR.

[3] Write a value corresponding to the

bit rate to BRR. Not necessary if

an external clock is used.

[4] Wait at least one bit interval, then

set the TE bit or RE bit in SCR to 1.

Also set the RIE, TIE, TEIE, and

MPIE bits.

Setting the TE and RE bits enables

the TxD and RxD pins to be used.

Figure 15.5 Sample SCI Initialization Flowchart

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