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HD64F2145 Datasheet(PDF) 143 Page - Renesas Technology Corp |
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HD64F2145 Datasheet(HTML) 143 Page - Renesas Technology Corp |
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143 / 829 page ![]() Rev. 2.0, 08/02, page 103 of 788 Program excution state Interrupt generated? NMI An interrupt with interrupt control level 1? IRQ0 IRQ1 IFBFI3 IRQ0 IRQ1 IFBFI3 UI = 0 Save PC and CCR I 1, UI 1 Read vector address Branch to interrupt handling routine Yes No Yes Yes Yes No No Yes No Yes No Yes Yes No No Yes Yes No Hold pending I = 0 I = 0 Yes Yes No No Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1 5.6.3 Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. |
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