HD64F2145 datasheet(215/829 Pages) RENESAS

215 / 829 page

Rev. 2.0, 08/02, page 175 of 788

8.6.2

Port 5 Data Register (P5DR)

P5DR stores output data for port 5 pins.

Bit

Bit Name

Initial Value

R/W

Description

—

All 1

—

Reserved

The initial value must not be changed.

P52DR

R/W

P51DR

R/W

P50DR

R/W

If a port 5 read is performed while P5DDR bits are

set to 1, the P5DR values are read directly,

regardless of the actual pin states. If a port 5 read

is performed while P5DDR bits are cleared to 0, the

pin states are read.

8.6.3

Pin Functions

• P52/SCK0/SCL0

The pin function is switched as shown below according to the combination of the CKE1 and

CKE0 bits in SCR of SCI_0, the C/

$ bit in SMR of SCI_0, the ICE bit in ICCR of IIC_0, and

the P52DDR bit.

ICE

CKE1

—

CKE0

—

P52DDR

——

Pin Function

P52

input pin

P52

output pin

SCK0 output

SCK0

input pin

SCL0

I/O pin

Note:* When this pin is used as the SCL0 I/O pin, bits CKE1 and CKE0 in SCR of SCI0 and bit C/

in SMR of SCI0 must all be cleared to 0.

SCL0 is an NMOS open-drain output, and has direct bus drive capability.

When set as the P52 output pin or SCK0 output pin, this pin is an NMOS push-pull output.

• P51/RxD0

The pin function is switched as shown below according to the combination of the RE bit in

SCR of SCI_0 and the P51DDR bit.

P51DDR

—

Pin Function

P51 input pin

P51 output pin

RxD0 input pin

HD64F2145 Datasheet(PDF) 215 Page - Renesas Technology Corp

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