HD64F2145 datasheet(228/829 Pages) RENESAS

228 / 829 page

Rev. 2.0, 08/02, page 188 of 788

8.10.2

Port 9 Data Register (P9DR)

P9DR stores output data for the port 9 pins.

Bit

Bit Name

Initial Value

R/W

Description

P97DR

R/W

P96DR

Undefined*

P95DR

R/W

P94DR

R/W

P93DR

R/W

P92DR

R/W

P91DR

R/W

P90DR

R/W

With the exception of P96, if a port 9 read is

performed while P9DDR bits are set to 1, the P9DR

values are read directly, regardless of the actual

pin states. If a port 9 read is performed while

P9DDR bits are cleared to 0, the pin states are

read.

For P96, the pin state is always read.

Note:* The initial value of bit 6 is determined according to the P96 pin state.

8.10.3

Pin Functions

• P97/:$,7/SDA0

The pin function is switched as shown below according to the combination of operating mode,

the WMS1 bit in WSCR, the ICE bit in ICCR of IIC_0, and the P97DDR bit.

Operating

Mode

Modes 1, 2, 3 (EXPE = 1)

Modes 2, 3 (EXPE = 0)

WMS1

—

ICE

—

P97DDR

—

Pin Function

P97 input

P97 output

SDA0 I/O

:$,7 input

P97 input

P97 output

SDA0 I/O

Note:* When this pin is set as the P97 output pin, it is an NMOS push-pull output. SDA0 is an

NMOS open-drain output, and has direct bus drive capability.

HD64F2145 Datasheet(PDF) 228 Page - Renesas Technology Corp

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