HD64F2145 datasheet(275/829 Pages) RENESAS

275 / 829 page

Rev. 2.0, 08/02, page 235 of 788

Table 10.3 summarizes the relationships between the CKS, CFS, and OS bit settings and the

resolution, base cycle, and conversion cycle. The PWM output remains fixed unless DADR

contains at least a certain minimum value.

Table 10.3

Settings and Operation (Examples when ø = 10 MHz)

Fixed DADR Bits

Bit Data

CKS

Resolution

T (µs)

CFS

Base

Cycle (µs)

Conversion

Cycle (µs)

L (if OS = 0)

H (if OS = 1)

Precisi-

(Bits)

32 10

Conversion

Cycle* (µs)

1638.4

0 0 409.6

06.4

Always low (or high)

(DADR = H'0001 to

H'03FD)

(Data value)

× T

(DADR = H'0401 to

H'FFFD)

0 0 0 0 102.4

1638.4

0 0 409.6

00.1

25.6

1638.4

Always low (or high)

(DADR = H'0003 to

H'00FF)

(Data value)

× T

(DADR = H'0103 to

H'FFFF)

0 0 0 0 102.4

3276.8

0 0 819.2

12.8

Always low (or high)

(DADR = H'0001 to

H'03FD)

(Data value)

× T

(DADR = H'0401 to

H'FFFD)

0 0 0 0 204.8

3276.8

0 0 819.2

10.2

51.2

3276.8

Always low (or high)

(DADR = H'0003 to

H'00FF)

(Data value)

× T

(DADR = H'0103 to

H'FFFF)

0 0 0 0 204.8

Note:* This column indicates the conversion cycle when specific DADR bits are fixed.

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