HD64F2145 datasheet(284/829 Pages) RENESAS

284 / 829 page

Rev. 2.0, 08/02, page 244 of 788

11.3.1

Free-Running Counter (FRC)

FRC is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS1 and

CKS0 in TCR. FRC can be cleared by compare-match A. When FRC overflows from H'FFFF to

H'0000, the overflow flag bit (OVF) in TCSR is set to 1. FRC should always be accessed in 16-bit

units; cannot be accessed in 8-bit units. FRC is initialized to H'0000.

11.3.2

Output Compare Registers A and B (OCRA, OCRB)

The FRT has two output compare registers, OCRA and OCRB, each of which is a 16-bit

readable/writable register whose contents are continually compared with the value in FRC. When

a match is detected (compare-match), the corresponding output compare flag (OCFA or OCFB) is

set to 1 in TCSR. If the OEA or OEB bit in TOCR is set to 1, when the OCR and FRC values

match, the output level selected by the OLVLA or OLVLB bit in TOCR is output at the output

compare output pin (FTOA or FTOB). Following a reset, the FTOA and FTOB output levels are 0

until the first compare-match. OCR should always be accessed in 16-bit units; cannot be accessed

in 8-bit units. OCR is initialized to H'FFFF.

11.3.3

Input Capture Registers A to D (ICRA to ICRD)

The FRT has four input capture registers, ICRA to ICRD, each of which is a 16-bit read-only

is detected, the current FRC value is transferred to the corresponding input capture register (ICRA

to ICRD). At the same time, the corresponding input capture flag (ICFA to ICFD) in TCSR is set

to 1. The FRC contents are transferred to ICR regardless of the value of ICF. The input capture

edge is selected by the input edge select bits (IEDGA to IEDGD) in TCR.

ICRC and ICRD can be used as ICRA and ICRB buffer registers, respectively, by means of buffer

enable bits A and B (BUFEA and BUFEB) in TCR. For example, if an input capture occurs when

ICRC is specified as the ICRA buffer register, the FRC contents are transferred to ICRA, and then

transferred to the buffer register ICRC.

To ensure input capture, the input capture pulse width should be at least 1.5 system clocks (ø) for a

single edge. When triggering is enabled on both edges, the input capture pulse width should be at

least 2.5 system clocks (ø).

ICRA to ICRD should always be accessed in 16-bit units; cannot be accessed in 8-bit units. ICR is

initialized to H'0000.

HD64F2145 Datasheet(PDF) 284 Page - Renesas Technology Corp