HT82V36

Rev. 1.30

5

June 29, 2004

Internal Register Descriptions

Register

Name

Address

Data Bits

A2

A1

A0

D8

D7

D6

D5

D4

D3

D2

D1

D0

Configuration

0000011

CDS on

Clamp

Voltage

Enable

Power

Down

Output

Delay

1byte

out

Reserved

0

0

1

Reserved

0

1

0

PGA

0

1

1

X

0

0

MSB

LSB

Reserved

1

0

0

Reserved

1

0

1

Offset

1

1

0

MSB

LSB

Reserved

1

1

1

Internal Register Map

D8

D7

D6

D5

D4

D3

D2

D1

D0

Set to 0 Set to 0 Set to 1 Set to 1

CDS operation Clamp bias Power-down

Output delay

1 byte out

(High-byte only)

1=CDS mode*

1=2.5V*

1=On

1=On

1=On

0=SHA mode

0=2V

0=Off (Normal)* 0=Off*

0=Off*

Configuration Register Settings

Note: * Power-on default value

PGA Gain Register

Bits D7 and D6 in the register must be set low, and bits D5 through D0 control the gain range in 64 increments. See fig-

ure for a graph of the PGA gain versus PGA register code. The coding for the PGA register is straight binary, with an all

zero words corresponding to the minimum gain setting (1x) and an all one word corresponding to the maximum gain

setting (5.85x).

The PGA has a gain range from 1x (0dB) to 5.85x (15.3dB), adjustable in 64 steps. The Figure shows the PGA gain as a

function of the PGA register code. Although the gain curve is approximately linear in dB, the gain in V/V varies in non-

linear proportion with the register code, according to the following the equation: Gain=

5.85

14.85(

63

G

63

)

+

´

-

Where G is the decimal value of the gain register contents, and varies from 0 to 63.

PGA Gain Transfer Function

1 2 1 6 2 0 2 4 2 8 3 2 3 6 4 0 4 4 4 8 5 2 5 6 6 0

0

4

8

6 3

1 5

1 2

9

6

3

0

5 . 8 5

5 . 0

4 . 0

3 . 0

2 . 0

1 . 0

P G A r e g i s t e r v a l u e - - D e c i m a l

´