2008. 8. 28

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SEMICONDUCTOR

TECHNICAL DATA

Revision No : 0

Bias Resistor Transistors

PNP Silicon Surface Mount Transistors

with Monolithic Bias Resistor Network

This new series of digital transistors is designed to replace a single

device and its external resistor bias network. The BRT (Bias Resistor

Transistor) contains a single transistor with a monolithic bias network

consisting of two resistors; a series base resistor and a base-emitter

resistor. The BRT eliminates these individual components by integrating

them into a single device. The use of a BRT can reduce both system

cost and board space. The device is housed in the SC-89 package

which is designed for low power surface mount applications.

• Simplifies Circuit Design

• Reduces Board Space

• Reduces Component Count

• The SC-89 package can be soldered using wave or reflow. The

modified gull-winged leads absorb thermal stress during soldering

eliminating the possibility of damage to the die.

•

SC-89

PIN 3

COLLECTOR

(OUTPUT)

PIN 2

EMITTER

(GROUND)

PIN 1

BASE

(INPUT)

We declare that the material of product compliance with

RoHS requirements.

Rating

Symbol

Value

Unit

Collector-Base Voltage

50

Vdc

Collector-Emitter Voltage

50

Vdc

Collector Current

100

mAdc

THERMAL CHARACTERISTICS

Rating

Symbol

Value

Unit

Total Device Dissipation,

FR−4 Board

Derate above 25

°C

200

1.6

mW

mW/

°C

Thermal Resistance,

Junction−to−Ambient

(Note 1)

600

°C/W

Total Device Dissipation,

FR−4 Board

Derate above 25

°C

300

2.4

mW

mW/

°C

Thermal Resistance,

Junction−to−Ambient

(Note 2)

400

°C/W

Junction and Storage Temperature Range

−55 to

+150

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1.

FR−4 @ Minimum Pad.

2.

FR−4 @ 1.0 ×1.0 Inch Pad.

DTA601~611,

DTA617, DTA622