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UTCL8115 Datasheet(PDF) 7 Page - Unisonic Technologies |
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UTCL8115 Datasheet(HTML) 7 Page - Unisonic Technologies |
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7 / 13 page ![]() UTC L8115 LINEAR INTEGRATED CIRCUIT UTC UNISONIC TECHNOLOGIES CO., LTD. 7 QW-R123-005,B FUNCTIONAL DESCRIPTION The UTC L8115 provides all the bias requirements for external FETs, including the generation of the negative supply required for gate biasing, from the single supply voltage.The diagram above shows a single stage from the UTC series. It contains 3 such stages. The negative rail generator is common to both devices. The drain voltage of the external FET QN is set by the UTC L8115 to its normal operating voltage. This is determined by the on board VD Set reference, the UTC L8115 this is nominally 2.2 volts whilst. The drain current taken by the FET is monitored by the low value resistor ID Sense. The amplifier driving the gateof the FET adjusts the gate voltage of QN so that the drain current taken matches the current called for by an external resistor RCAL. Since the FET is a depletion mode transistor, it is often necessary to drive its gate negative with respect to groundto obtain the required drain current. To provide this capability powered from a single positive supply, the deviceincludes a low current negative supply generator. This generator uses an internal oscillator and two external capacitors, CNB and CSUB. The following schematic shows the function of the VPOL input. Only one of the two external FETs numberd Q1 and Q2 are powered at any one time,their selection is controlled by the input VPOL.This input is designed to be wired to the power input of the LNB via a high value(10k) resistor.With the input voltage of the LNB set at or below 14V,.FET Q2 will be enabled.With the input voltage at or above 15.5V,FET Q1 will be enabled.The disabled FET has its gate driven low and its drain terminal is switched open circuit. It is permissible to commect the drain pins D1 and D2 together if required by the application circuit;this is done internally in the SSOP-16(150mil) version.FET number Q3 is always active regardless of the voltage applied to VPOL. Enable Drain Voltage & Current Controller D1 Q1 G1 20μA - + VSUB Enable Drain Voltage & Current Controller D2 Q2 G2 20μA VSUB Enable Drain Voltage & Current Controller D3 Q3 G3 20μA VSUB 14.75V Reference VPOL Input For SSOP-20(150mil) Package |
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