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H5TQ2G43CFR-RDC Datasheet(PDF) 30 Page - Hynix Semiconductor

Part # H5TQ2G43CFR-RDC
Description  2Gb DDR3 SDRAM
PDF  33 Pages
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

H5TQ2G43CFR-RDC Datasheet(HTML) 30 Page - Hynix Semiconductor

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Rev. 1.0 / Apr. 2013
30
DDR3-1866 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 32.
Speed Bin
DDR3-1866M
Unit
Note
CL - nRCD - nRP
13-13-13
Parameter
Symbol
min
max
Internal read command
to first data
tAA
13.91
(13.125)5,14
20
ns
ACT to internal read or
write delay time
tRCD
13.91
(13.125)5,14
—ns
PRE command period
tRP
13.91
(13.125)5,14
—ns
ACT to PRE command
period
tRAS
34
9 * tREFI
ns
ACT to ACT or PRE
command period
tRC
47.91
(47.125)5,14
-ns
CL = 5
CWL = 5
tCK(AVG)
Reserved
ns
1,2,3,4,9
CWL = 6,7,8,9 tCK(AVG)
Reserved
ns
4
CL = 6
CWL = 5
tCK(AVG)
2.5
3.3
ns
1,2,3,9
CWL = 6
tCK(AVG)
Reserved
ns
1,2,3,4,9
CWL = 7,8,9
tCK(AVG)
Reserved
ns
4
CL = 7
CWL = 5
tCK(AVG)
Reserved
ns
4
CWL = 6
tCK(AVG)
1.875
< 2.5
ns
1,2,3,4,9
CWL = 7,8,9
tCK(AVG)
Reserved
ns
4
CL = 8
CWL = 5
tCK(AVG)
Reserved
ns
4
CWL = 6
tCK(AVG)
1.875
< 2.5
ns
1,2,3,9
CWL = 7
tCK(AVG)
Reserved
ns
1,2,3,4,9
CWL = 8,9
tCK(AVG)
Reserved
ns
4
CL = 9
CWL = 5, 6
tCK(AVG)
Reserved
ns
4
CWL = 7
tCK(AVG)
1.5
<1.875
ns
1,2,3,4,9
CWL = 8
tCK(AVG)
Reserved
ns
1,2,3,4,9
CWL = 9
tCK(AVG)
Reserved
ns
4
CL = 10
CWL = 5, 6
tCK(AVG)
Reserved
ns
4
CWL = 7
tCK(AVG)
1.5
<1.875
ns
1,2,3,9
CWL = 8
tCK(AVG)
Reserved
ns
1,2,3,4,9
CL = 11
CWL = 5,6,7
tCK(AVG)
Reserved
ns
4
CWL = 8
tCK(AVG)
1.25
<1.5
ns
1,2,3,4,9
CWL = 9
tCK(AVG)
Reserved
ns
1,2,3,4
CL = 12
CWL = 5,6,7,8 tCK(AVG)
Reserved
ns
4
CWL = 9
tCK(AVG)
Reserved
ns
1,2,3,4
CL = 13
CWL = 5,6,7,8 tCK(AVG)
Reserved
ns
4
CWL = 9
tCK(AVG)
1.07
<1.25
ns
1, 2, 3
Supported CL Settings
6, 7, 8, 9, 10, 11, 13
nCK
Supported CWL Settings
5, 6, 7, 8, 9
nCK



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