VSC8504-02 datasheet(39/131 Pages) MICROSEMI

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Functional Descriptions

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

Blink is a 50% duty cycle oscillation of asserting and de-asserting an LED pin. Pulse-stretch guarantees

that an LED is asserted and de-asserted for a specific period of time when activity is either present or not

present. These rates can also be configured using a register setting.

3.13.3.3 Rate of LED Blink or Pulse-Stretch

This behavior controls the LED blink rate or pulse-stretch length when blink/pulse-stretch is enabled on

an LED pin. The blink rate, which alternates between a high and low voltage level at a 50% duty cycle,

can be set to 2.5 Hz, 5 Hz, 10 Hz, or 20 Hz. For pulse-stretch, the rate can be set to 50 ms, 100 ms,

200 ms, or 400 ms. The blink rate selection for PHY0 globally sets the rate used for all LED pins on all

PHY ports.

3.13.3.4 LED Pulsing Enable

To provide additional power savings, the LEDs (when asserted) can be pulsed at 5 kHz with a

programmable duty cycle through register 25G bits 15:8. For duty cycle details, see Table 87, page 84.

3.13.3.5 LED Blink After Reset

The LEDs will blink for one second after power-up and after any time all resets have been de-asserted.

This can be disabled through register 19E1, bit 11 = 0.

3.13.3.6 Fiber LED Disable

This bit controls whether the LEDs indicate the fiber and copper status (default) or the copper status only.

3.13.3.7 Pulse Programmable Control

These bits add the ability to width and frequency of LED pulses. This feature facilitates power reduction

options.

3.13.3.8 Fast Link Failure

For more information about this feature, see Fast Link Failure Indication, page 29.

3.13.4

Basic Serial LED Mode

Optionally, the VSC8504-02 can be configured so that access to all its LED signals is available through

two pins. This option is enabled by setting LED0 on PHY0 to serial LED mode in register 29, bits 7:0 to

0xDD. When setting 3:0 to 0xD on the serial data signal is enabled, setting 7:4 to 0xD enables the serial

clock. When serial LED mode is enabled, the LED0_0 pin becomes the serial data pin, and the LED1_0

pin becomes the serial clock pin. All other LED pins can still be configured normally. The serial LED

mode clocks the 48 LED status bits on the rising edge of the serial clock.

The LED behavior settings can also be used in serial LED mode. The controls are used on a per-PHY

basis, where the LED combine and LED blink or pulse-stretch setting of LED0_n for each PHY is used to

control the behavior of each bit of the serial LED stream for each corresponding PHY. To configure LED

behavior, set device register 30.

The following table shows the 48-bit serial output bitstream of each LED signal. The individual signals

can be clocked in the following order.

Table 9 •

LED Serial Bitstream Order

Output

PHY0 PHY1 PHY2 PHY3

Link/activity

Link1000/activity

Link100/activity

Link10/activity

Fiber link/activity

Duplex/collision

Collision

VSC8504-02 Datasheet(PDF) 39 Page - Microsemi Corporation

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