AD5379

Rev. 0 | Page 14 of 28

Pin

Function

RESET

Asynchronous Digital Reset Input (falling edge sensitive). If unused, RESET may be left unconnected; an internal pull-

up resistor (1 MΩ) ensures that the RESET input is held high. The function of this pin is equivalent to that of the

power-on reset generator. When this pin is taken low, the AD5379 state machine initiates a reset sequence to digitally

reset x1, m, c, and x2 registers to their default power-on values. This sequence takes 100 µs (typ). Furthermore, the

input to each of the DAC output buffer stages, VOUT0 to VOUT39, is switched to the externally set potential on the

relevant REFGND pin. During RESET, BUSY goes low and the parallel interface is disabled. All LDAC pulses are ignored

until BUSY goes high. When RESET is taken high again, the DAC ouputs remain at REFGND until LDAC is taken low.

REFGNDA1

Reference Ground for DACs 0 to 7. VOUT0 to VOUT7 are referenced to this voltage.

REFGNDA2

Reference Ground for DACs 8 and 9. VOUT8 and VOUT9 are referenced to this voltage.

REFGNDB1

Reference Ground for DACs 10 to 17. VOUT10 to VOUT17 are referenced to this voltage.

REFGNDB2

Reference Ground for DACs 18 and 19. VOUT18 and VOUT19 are referenced to this voltage.

REFGNDC1

Reference Ground for DACs 20 to 27. VOUT20 to VOUT27 are referenced to this voltage.

REFGNDC2

Reference Ground for DACs 28 and 29. VOUT28 and VOUT29 are referenced to this voltage.

REFGNDD1

Reference Ground for DACs 30 to 37. VOUT30 to VOUT37 are referenced to this voltage.

REFGNDD2

Reference Ground for DACs 38 and 39. VOUT38 and VOUT39 are referenced to this voltage.