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Prebias Startup Capability

Start up

Period

UVLO

Threshold

V (5 V/Div)

I

V

(1 V/Div)

O

V 1 (1 V/Div)

O

V 2 (1 V/Div)

O

I 2 (5 A/Div)

O

t - Time = 10 s/Div

m

PTH12060W/L

SLTS217D–MAY 2003–REVISED OCTOBER 2005

The capability to start up into an output prebias condition is now available to all the 12-V input, PTH series of

A prebias startup condition occurs as a result of an external voltage being present at the output of a power

module prior to its output becoming active. This often occurs in complex digital systems when current from

another power source is backfed through a dual-supply logic component, such as an FPGA or ASIC. Another

path might be via clamp diodes, sometimes used as part of a dual-supply power-up sequencing arrangement. A

prebias can cause problems with power modules that incorporate synchronous rectifiers. This is because under

most operating conditions, such modules can sink as well as source output current. The 12-V input PTH modules

all incorporate synchronous rectifiers, but does not sink current during startup, or whenever the Inhibit pin is held

low. Startup includes an initial delay (approximately 8ms–15 ms), followed by the rise of the output voltage under

Conditions for Prebias Holdoff

In order for the module to allow an output prebias voltage to exist (and not sink current), certain conditions must

be maintained. The module holds off a prebias voltage when the Inhibit pin is held low, and whenever the output

is allowed to rise under soft-start control. Power up under soft-start control occurs upon the removal of the

ground signal to the Inhibit pin (with input voltage applied), or when input power is applied with Auto-Track

its Inhibit), the input voltage must always be greater than the applied prebias source. This condition must exist

The soft-start period is complete when the output begins rising above the prebias voltage. Once it is complete

the module functions as normal, and sinks current if a voltage higher than the nominal regulation value is applied

to its output.

Note: If a prebias condition is not present, the soft-start period is complete when the output voltage has risen

to either the set-point voltage, or the voltage applied at the module's Track control pin, whichever is lowest.

to its output.

Demonstration Circuit

the prebias voltage, which is passed from the VCCIO to the VCORE voltage rail through the ASIC. Note that the

prebias.

Figure 18. PTH12020W Startup

Figure 19. Prebias Startup Waveforms

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