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LP3470A438 Datasheet(PDF) 9 Page - Texas Instruments |
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LP3470A438 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 16 page ![]() + ± Reference GND VCC RESET GND RESET LOGIC TIMER SRT VCC1 R SRT 9 LP3470A www.ti.com SNVSBF5B – JULY 2019 – REVISED NOVEMBER 2019 Product Folder Links: LP3470A Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated 8 Detailed Description 8.1 Overview The LP3470A micropower voltage supervisory circuit provides a simple solution to monitor the power supplies in microprocessor and digital systems and provides a reset controlled by the factory-programmed reset threshold on the VCC supply voltage pin. When the voltage declines below the reset threshold, the reset signal is asserted and remains asserted for an interval programmed by an external capacitor after VCC has risen above the threshold voltage. The reset threshold options are 2.63 V, 2.75 V, 2.93 V, 3.08 V, 3.65 V, 4 V, 4.38 V, 4.63 V. 8.2 Functional Block Diagram 8.3 Feature Description 8.3.1 RESET Time-Out Period The reset time delay can be set to a minimum value of 50 µs by leaving the SRT pin floating, or a maximum value of approximately 6.2 seconds by connecting 10 µF delay capacitor. The reset time delay (tD) can be programmed by connecting a capacitor no larger than 10 µF between SRT pin and GND. The relationship between external capacitor (CSRT) in Farads at SRT pin and the time delay (tD) in seconds is given by Equation 1. tD = -ln (0.29) x RSRT x CSRT + tD (no cap) (1) Equation 1 is simplified to Equation 2 by plugging RSRT and tD(no cap) given in Electrical Characteristics section: tD = 618937 x CSRT + 50 µs (2) Equation 3 solves for external capacitor value (CSRT) in units of Farads where tD is in units of seconds CSRT = (tD- 50 µs) ÷ 618937 (3) The reset delay varies according to three variables: the external capacitor variance (CSRT), SRT pin internal resistance (RSRT) provided in the Electrical Characteristics table, and a constant. The minimum and maximum variance due to the constant is shown in Equation 5 and Equation 6. tD (minimum) = -ln (0.36) x RSRT (min) x CSRT (min) + tD (no cap, min) (4) tD (maximum) = -ln (0.26) x RSRT (max) x CSRT (max) + tD (no cap, max) (5) |
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