A43E06161 datasheet(2/46 Pages) AMICC

2 / 46 page

A43E06161

Preliminary

512K X 16 Bit X 2 Banks Synchronous DRAM

PRELIMINARY

(July, 2005, Version 0.1)

AMIC Technology, Corp.

Features

Low power supply

- VDD: 1.8V

- VDDQ: 1.8V

LVCMOS compatible with multiplexed address

Dual banks / Pulse

RAS

MRS cycle with address key programs

- CAS Latency (2,3)

- Burst Length (1,2,4,8 & full page)

- Burst Type (Sequential & Interleave)

All inputs are sampled at the positive going edge of the

system clock

Deep Power Down Mode

Clock Frequency: 105MHz @ CL=3 (-95)

133MHz @ CL=3 (-75)

Industrial operating temperature range: -40ºC to +85ºC

for –U

Pb-Free type for -F

Burst Read Single-bit Write operation

DQM for masking

Auto & self refresh

32ms refresh period (2K cycle)

Available in 50-pin TSOP(II) package

General Description

The A43E06161 is 16,777,216 bits synchronous high data

rate Dynamic RAM organized as 2 X 524,288 words by 16

bits, fabricated with AMIC’s high performance CMOS

technology. Synchronous design allows precise cycle control

with the use of system clock. I/O transactions are possible on

every

clock

cycle.

Range

operating

frequencies,

programmable latencies allows the same device to be useful

for a variety of high bandwidth, high performance memory

system applications.

Pin Configuration

TSOP (II)

A43E06161V

50 49 48 47 46 45 44 43 42 41

38 37 36 35 34 33 32 31 30 29 28 27 26

567

9 10

13 14 15 16 17 18 19 20 21 22 23 24 25

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