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BU21180FS Datasheet(PDF) 21 Page - Rohm

Part # BU21180FS
Description  Capacitive Switch Controller IC
PDF  44 Pages
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Manufacturer  ROHM [Rohm]
Direct Link  http://www.rohm.com
Logo ROHM - Rohm

BU21180FS Datasheet(HTML) 21 Page - Rohm

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© 2017 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111
• 15 • 001
BU21180FS
TSZ02201-0L5L0F300930-1-2
06.Aug.2018 Rev.002
0x4F: Multiple Pattern Switches ON Detection
Name:
DET_MULT_ON
Address:
0x4F
Description:
This register shows that the state of multiple pattern switches changed from OFF to ON simultaneously
within the fixed time. The bit
“INT_MULT_ON” in the register “Interrupt Factor” shows the OR of this register.
This is cleared by setting 0 to the register
“Clear Multiple Pattern Switches ON Detection”. The fixed time is
set by the register
“Switch Detection Time”. The multiple pattern switch combinations are set by the register
“Multiple Pattern Switches Assignment”.
0: Multiple Pattern Switches ON - undetected
1: Multiple Pattern Switches ON - detected
Address
R/W
Initial
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x4F
R
0x00
DET_MULT
_ON_H
DET_MULT
_ON_G
DET_MULT
_ON_F
DET_MULT
_ON_E
DET_MULT
_ON_D
DET_MULT
_ON_C
DET_MULT
_ON_B
DET_MULT
_ON_A
0x50: Multiple Pattern Switches OFF Detection
Name:
DET_MULT_OFF
Address:
0x50
Description:
This register shows that that the state of multiple pattern switches changed from ON to OFF simultaneously.
The bit
“INT_MULT_OFF” in the register “Interrupt Factor” shows the OR of this register. This is cleared by
setting 0 to the register
“Clear Multiple Pattern Switches OFF Detection”.
0: Multiple Pattern Switches OFF - undetected
1: Multiple Pattern Switches OFF - detected
Address
R/W
Initial
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x50
R
0x00
DET_MULT
_OFF_H
DET_MULT
_OFF_G
DET_MULT
_OFF_F
DET_MULT
_OFF_E
DET_MULT
_OFF_D
DET_MULT
_OFF_C
DET_MULT
_OFF_B
DET_MULT
_OFF_A
0x51-0x53: Unexpected Long Press Detection
Name:
DET_UNKNOWN
Address:
0x51-0x53
Description:
These registers show that unexpected long press was detected. The bit
“INT_UNK” in the register “Interrupt
Factor
” shows the OR of these registers. These are cleared by setting 0 to the register “Clear Unexpected
Long Press Detection
”. The unexpected long press duration is set by the register “Unexpected Long Press
Detection Time
”.
0: Unexpected Long Press - undetected
1: Unexpected Long Press - detected
Address
R/W
Initial
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x51
R
0x00
DET_UNK
_CS7
DET_UNK
_CS6
DET_UNK
_CS5
DET_UNK
_CS4
DET_UNK
_CS3
DET_UNK
_CS2
DET_UNK
_CS1
DET_UNK
_CS0
0x52
R
0x00
DET_UNK
_CS15
DET_UNK
_CS14
DET_UNK
_CS13
DET_UNK
_CS12
DET_UNK
_CS11
DET_UNK
_CS10
DET_UNK
_CS9
DET_UNK
_CS8
0x53
R
0x00
-
-
-
-
DET_UNK
_CS19
DET_UNK
_CS18
DET_UNK
_CS17
DET_UNK
_CS16
0x54-0x56: Switch ON / OFF State
Name:
SW_STATE
Address:
0x54-0x56
Description:
These registers show ON / OFF state of switch. These states are the result filtered by the register
“Oversampling”.
0: OFF state
1: ON state
Address
R/W
Initial
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x54
R
0x00
SW_STAT
_CS7
SW_STAT
_CS6
SW_STAT
_CS5
SW_STAT
_CS4
SW_STAT
_CS3
SW_STAT
_CS2
SW_STAT
_CS1
SW_STAT
_CS0
0x55
R
0x00
SW_STAT
_CS15
SW_STAT
_CS14
SW_STAT
_CS13
SW_STAT
_CS12
SW_STAT
_CS11
SW_STAT
_CS10
SW_STAT
_CS9
SW_STAT
_CS8
0x56
R
0x00
-
-
-
-
SW_STAT
_CS19
SW_STAT
_CS18
SW_STAT
_CS17
SW_STAT
_CS16



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