ST7232A datasheet(10/154 Pages) STMICROELECTRONICS

Part #	ST7232A

Description	8-BIT MCU WITH 8K FLASH/ROM, ADC, 4 TIMERS, SPI, SCI INTERFACE

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

Direct Link	http://www.st.com

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10 / 154 page

ST7232A

10/154

Notes:

1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up

column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,

else the configuration is floating interrupt input.

2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to VDD

are not implemented). See See “I/O PORTS” on page 40. and Section 12.8 I/O PORT PIN CHARACTER-

ISTICS for more details.

3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscil-

lator; see Section 1 INTRODUCTION and Section 12.5 CLOCK AND TIMING CHARACTERISTICS for

more details.

4. On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up con-

figuration after reset. The configuration of these pads must be kept at reset state to avoid added current

consumption.

5. For details refer to Section 12.8.1 on page 126

15 18 PC7/SS/AIN15

I/O CT

X

XX

X

Port C7

SPI Slave

Select (ac-

tive low)

ADC Analog

Input 15

16 19 PA3 (HS)

I/O CT HS

X

ei0

X

Port A3

17 20 PA4 (HS)

I/O CT HS

X

XX

X

Port A4

18 21 PA6 (HS)

I/O CT HS

X

TPort A6 1)

19 22 PA7 (HS)

I/O CT HS

X

TPort A7 1)

20 23 VPP /ICCSEL

I

Must be tied low. In the flash pro-

gramming mode, this pin acts as the

programming voltage input VPP. See

Section 12.9.2 for more details. High

voltage must not be applied to ROM

devices.

21 24 RESET

I/O CT

Top priority non maskable interrupt.

22 25 VSS_2

S

Digital Ground Voltage

23 26 OSC2

O

Resonator oscillator inverter output

24 27 OSC1

I

External clock input or Resonator os-

cillator inverter input

25 28 VDD_2

S

Digital Main Supply Voltage

26 29 PE0/TDO

I/O CT

X

Port E0

SCI Transmit Data Out

27 30 PE1/RDI

I/O CT

X

Port E1

SCI Receive Data In

28 31 PB0

I/O CT

X

ei2

X

Port B0

Caution: Negative cur-

rent injection not al-

lowed on this pin5)

29 32 PB3

I/O CT

X

ei2

X

Port B3

30 1

PB4 (HS)

I/O CT HS

X

ei3

X

Port B4

31 2

PD0/AIN0

I/O CT

X

Port D0

ADC Analog Input 0

32 3

PD1/AIN1

I/O CT

X

Port D1

ADC Analog Input 1

Pin N°

Pin Name

Level

Port

Main

function

(after

reset)

Alternate Function

Input

Output

1

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