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STV5346D/H Datasheet(PDF) 10 Page - STMicroelectronics

Part # STV5346D/H
Description  MONOCHIP TELETEXT DECODER WITH 8 INTEGRATED PAGES
PDF  21 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STV5346D/H Datasheet(HTML) 10 Page - STMicroelectronics

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FUNCTIONAL DESCRIPTION (continued)
III - I
2C Bus Register Map (see Table 2)
Registers R0 to R10 are write only whilst R11A is a
read/write and R11B is a read only register respect
to the microprocessor.
The automatic succession on a byte basis is indi-
cated by the arrows in Table 2.
In the normal operating mode TB should be set to
logic level 0.
After power-up the contents of the registers are as
follows : all bits in registers R0 to R11A are cleared
to zero with the exception of bits D0 and D1 in
registers R5 and R6 which are set to logical one.
After power-up all the memory bytes are preset to
hexadecimal value 20H (space) with the exception
of the byte corresponding to row 0 of column 7 of
chapter 0 which is set to the value corresponding
to ”alpha white” hexadecimal value 07H.
D7
D6
D5
D4
D3
D2
D1
D0
X24
POSITION
FREE
RUNNING
PLL
(1)
DISABLE
ROLLING
HEADER
(1)
EVEN
OFF
(1)
SEL 11B
R0
Mode 0
(1)
7 + P/
8 BIT
ACQ.
ON/OFF
GHOST
ROW
ENABLE
DEW/
FULL
FIELD
TCS
ON
T1
T0
R1
Mode 1
(1)
BANK
SELECT
A2
ACQ.
CCT
A1
ACQ.
CCT
A0
TB
START
COLUMN
SC2
START
COLUMN
SC1
START
COLUMN
SC0
R2
Page request address
(1)
(1 )
(1)
PRD4
PRD3
PRD2
PRD1
PRD0
R3
Page request data
(1)
(1 )
(1)
(1)
(1)
A2
A1
A0
R4
Display chapter
BKGND
OUT
BKGND
IN
COR
OUT
COR
IN
TEXT
OUT
TEXT
IN
PON
OUT
PON
IN
R5
Display control (normal)
BKGND
OUT
BKGND
IN
COR
OUT
COR
IN
TEXT
OUT
TEXT
IN
PON
OUT
PON
IN
R6
Display control
(newsflash / subtitle)
STATUS
ROW
BTM/TOP
CURSOR
ON/OFF
CONCEAL/
REVEAL
TOP/
BOTTOM
SINGLE/
DOUBLE
HEIGHT
BOX ON
24
BOX ON
1-23
BOX ON
0
R7
Display mode
(1)
(1 )
(1)
(1)
CLEAR
MEM.
A2
A1
A0
R8
Active chapter
(1)
(1 )
(1)
R4
R3
R2
R1
R0
R9
Active row
(1)
(1 )
C5
C4
C3
C2
C1
C0
R10
Active column
D7
(R/W)
D6
(R/W)
D5
(R/W)
D4
(R/W)
D3
(R/W)
D2
(R/W)
D1
(R/W)
D0
(R/W)
R11A
Active data
60Hz
0
0
0
0
0
0
VCS
QUAL
R11B
Status
↵
↵
↵
↵
↵
(1) Reserved register bits : must be set to 0
↵
↵
↵
↵
Table 2 : Register specification
STV5346 - STV5346/H - STV5346/T
10/21



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