TAS5504 datasheet(13/96 Pages) TI

13 / 96 page

Introduction

SLES123 − October 2004

TAS5504

TERMINAL

DESCRIPTION

TERMIN-

ATION

5-V

TOLERANT

I/O

NO.

DESCRIPTION

TERMIN-

ATION

5-V

TOLERANT

I/O

NAME

VRD_PLL

Voltage reference for PLL digital supply 1.8 V. A pin-out of the internally regulated

1.8-V power used by PLL logic. A 0.1-µF low ESR capacitor should be connected

between this terminal and AVSS_PLL. This terminal must not be used to power

external devices.

AVSS_PLL

Analog ground for PLL. This terminal should reference the same ground as power

terminal DVSS, but to achieve low PLL jitter; ground noise at this terminal must be

minimized. The availability of the AVSS terminal allows a designer to use

optimizing techniques such as star ground connections, separate ground planes,

or other quiet ground distribution techniques to achieve a quiet ground reference

at this terminal.

AVDD_PLL

3.3-V analog power supply for PLL This terminal can be connected to the same

power source used to drive power terminal DVSS, but to achieve low PLL jitter, this

terminal should be bypassed to AVSS_PLL with a 0.1-µF low-ESR capacitor.

VBGAP

Band gap voltage reference. A pin-out of the internally regulated 1.2-V reference.

Typically has a 1-nF low ESR capacitor between VBGAP and AVSS_PLL. This

terminal must not be used to power external devices.

RESET

5 V

Pull up

System reset input, active low. A system reset is generated by applying a logic low

to this terminal. RESET is an asynchronous control signal that restores the

TAS5504 to its default conditions, sets the valid output low, and places the PWM

in the hard mute (M) state. Master volume is immediately set to full attenuation.

Upon the release of RESET, if PDN is high, the system performs a 4−5 ms. device

initialization and set the volume at mute.

HP_SEL

5 V

Pull up

Headphone in/out selector. When a logic low is applied, the headphone is selected

(speakers are off). When a logic high is applied, speakers are selected –

headphone is off.

PDN

5 V

Pull up

Power down, active low. PDN powers down all logic and stops all clocks whenever

a logic low is applied. The internal parameters are preserved through a power down

cycle, as long as a RESET is not active. The duration for system recovery from

power down is 100 ms.

MUTE

5 V

Pull up

Soft mute of outputs, active low (Muted signal = a logic low, normal operation = a

logic high) The mute control provides a noiseless volume ramp to silence.

Releasing mute provides a noiseless ramp to previous volume.

DVDD

Digital power 3.3-V supply for digital core and most of I/O buffers

DVSS

Digital ground for digital core and most of I/O buffers

VR_DPLL

Voltage reference for digital PLL supply 1.8 V. A pin-out of the internally regulated

1.8-V power used by digital PLL logic. A 0.1−µF low ESR capacitor should be

connected between this terminal and DVSS_CORE. This terminal must not be

used to power external devices.

OSC_CAP

Oscillator capacitor

XTL_OUT

XTL_OUT and XTL_IN are the only LVCMOS terminals on the device. They

provide a reference clock for the TAS5504 via use of an external fundamental mode

crystal. XTL_OUT is the 1.8-V output drive to the crystal. See Note 4 for the

recommended crystal type.

XTL_IN

XTL_OUT and XTL_IN are the only LVCMOS terminals on the device. They

provide a reference clock for the TAS5504 via use of an external fundamental mode

crystal. XTL_IN is the 1.8-V input port for the oscillator circuit. See Note 4 for the

recommended crystal type.

RESERVED

Connect to digital ground

RESERVED

Connect to digital ground

RESERVED

Connect to digital ground

SDA

DIO

5 V

I2C serial control data interface input / output

SCL

5 V

I2C serial control clock input output

LRCLK

5 V

Serial audio data left / right clock (sampling rate clock)

SCLK

5 V

Serial audio data clock (shift clock) SCLKIN is the serial audio port (SAP) input data

bit clock that is supplied to the serial bit clock to other I2S bus.

TAS5504 Datasheet(PDF) 13 Page - Texas Instruments

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