SLC90E66 datasheet(21/257 Pages) SMSC

21 / 257 page

SMSC DS – SLC90E66

Page 21

Rev. 07/10/2002

NAME

TYPE

DESCRIPTION

IOCHRDY

I/O

I/O CHANNEL READY. When asserted, the signal indicates that wait states are

required to complete the cycle. This signal is normally high. IOCHRDY is an input when

the SLC90E66 owns the ISA Bus and the CPU or a PCI agent is accessing an ISA slave,

or during DMA transfers. It becomes an output when an external ISA master owns the

ISA Bus and is accessing DRAM or a SLC90E66 register. As an output, the signal is

driven low (negated) from the falling edge of the ISA commands by the SLC90E66. After

data is available for an ISA master read or the SLC90E66 latches the data for a write

cycle, IOCHRDY is asserted for 70ns. After 70 ns, IOCHRDY is floated. The 70 ns

includes both the drive time and the time it takes the SLC90E66 to float IOCHRDY. The

SLC90E66 does not drive the signal when it is not the target of a bus master cycle.

During Reset: High-Z

After Reset: High-Z

During POS: High-Z

nIOCS16

16-BIT I/O CHIP SELECT. This signal is driven by ISA resources to indicate that the ISA

I/O device supports 16-bit I/O bus cycles.

nIOR

I/O

I/O READ. nIOR is the command to an ISA I/O device to indicate that the slave may

drive data on SD[15-0]. The I/O device must hold the data valid until after nIOR is

negated. nIOR is an output when the SLC90E66 owns the ISA Bus. nIOR is an input

when an external ISA master owns the ISA Bus.

During Reset: High-Z

After Reset: High

During POS: High

nIOW

I/O

IO/ WRITE. nIOW is the command to an ISA I/O device indicating that the I/O device

may latch data from the ISA data bus (SD[15-0]). nIOW is an output when the

SLC90E66 owns the ISA Bus. nIOW is an input when an external ISA master owns the

ISA bus.

During Reset: High-Z

After Reset: High

During POS: High

nMEMCS16

I/O

MEMORY CHIP SELECT 16. nMEMCS16 is a decode of LA[23-17] without any

qualification of the command signals. ISA devices that are 16-bit memory devices assert

this signal. The SLC90E66 ignores nMEMCS16 during I/O and refresh cycles. It is used

by byte-swap logic during DMA cycles. This signal is an input when the SLC90E66

owns the ISA Bus. This signal is an output when an ISA master owns the ISA Bus. The

SLC90E66 drives this signal low during ISA master to PCI memory cycles.

During Reset: High-Z

After Reset: High-Z

During POS: High-Z

nZEROWS

ZERO WAIT STATES. The signal is asserted by an ISA slave after the address and

command signals are decoded to indicate that the current cycle can be shortened. A 16-

Bit ISA memory cycle can be reduced to two SYSCLKs. An 8-Bit memory or I/O cycle

can be reduced to three SYSCLKs. nZEROWS has no effect on 16-Bit I/O cycles.

If IOCHRDY is negated and nZEROWS is asserted during the same clock, then

nZEROWS is ignored and wait states are added while IOCHRDY is negated.

RSTDRV

RESET DRIVE. The SLC90E66 asserts RSTDRV to reset devices that reside on the

ISA/EIO bus. The SLC90E66 asserts the signal during hard reset and during power-up.

RSTDRV is asserted during power-up and negated after PWROK is driven active. It is

also driven active for a minimum of 1ms if a hard reset has been programmed in the RC

During Reset: High

After Reset: Low

During POS: Low

SLC90E66 Datasheet(PDF) 21 Page - SMSC Corporation

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