13

Applications Information

Functional Description

Figure 23 shows the primary

functional blocks of the HCPL-

7850. In operation, the sigma-

delta modulator converts the

analog input signal into a high-

speed serial bit stream. The time

average of this bit stream is

directly proportional to the input

signal. This stream of digital data

is encoded and optically

transmitted to the detector

circuit. The detected signal is

decoded and converted back into

an analog signal, which is filtered

to obtain the final output signal.

Figure 25. Single-Supply Post-Amplifier Circuit.

Figure 26. Top Layer of Printed

Circuit Board Layout.

Figure 27. Bottom Layer of a Printed

Circuit Board Layout.

Application Circuit

The recommended application

circuit is shown in Figure 24. A

floating power supply (which in

many applications could be the

same supply that is used to drive

the high-side power transistor) is

regulated to 5 V using a simple

three-terminal voltage regulator

(U1). The voltage from the

current sensing resistor, or shunt

(Rsense), is applied to the input

of the HCPL-7850 through an RC

anti-aliasing filter (R5, C3). And

finally, the differential output of

the isolation amplifier is

converted to a ground-referenced

single-ended output voltage with

a simple differential amplifier

circuit (U3 and associated

components). Although the

application circuit is relatively

simple, a few recommendations

should be followed to ensure

optimal performance.

Supplies and Bypassing

As mentioned above, an

inexpensive three-terminal

regulator can be used to reduce

the gate-drive power supply

voltage to 5 V. To help attenuate

high frequency power supply

noise or ripple, a resistor or

0.1 µF

+5 V

VOUT

8

7

6

1

3

U2

5

2

4

R1

10.0 K

+5 V

C8

0.1 µF

–

+

MC34071

R3

10.0 K

HCPL-7850

C4

R4B

20.0 K

C6

150 pF

U3

R4A

20.0 K

+5 V

C5

150 pF

R2

10.0 K

C3

C2

C4

R5

Figure 28. Operating Circuit for Burn-In and Steady State Life Tests.

1

2

3

4

8

7

6

5

VDD

VIN+

VIN–

GND

VDD

VOUT+

VOUT–

GND

+

–

+

–

27

Ω

27

Ω

1 k

1 k

1 k

1 k

(+)

(–)

VDD

5.5 VDC

0.1 µF