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TLV9352IPWR Datasheet(PDF) 21 Page - Texas Instruments |
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TLV9352IPWR Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 34 page ![]() V- OUT GND GND GND NC ±IN +IN V± V+ OUTPUT NC NC VS+ VS± GND Ground (GND) plane on another layer VOUT VIN GND Run the input traces as far away from the supply lines as possible RF RG Place components close to device and to each other to reduce parasitic errors Use low-ESR, ceramic bypass capacitor GND Use a low-ESR, ceramic bypass capacitor + VIN VOUT RG RF 21 TLV9352 www.ti.com SBOS994 – NOVEMBER 2019 Product Folder Links: TLV9352 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated 10.2 Layout Example Figure 6. Schematic Representation Figure 7. Operational Amplifier Board Layout for Noninverting Configuration Figure 8. Example Layout for SC70 (DCK) Package |
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