HT36A4

Rev. 1.00

9

July 2, 2003

Interrupt

The HT36A4 provides two internal Timer Counter inter-

rupts on each bank. The Interrupt Control register

(INTC;0BH) contains the interrupt control bits that sets

the enable/disable and the interrupt request flags.

Once an interrupt subroutine is serviced, all other inter-

rupts will be blocked (by clearing the EMI bit). This

scheme may prevent any further interrupt nesting. Other

interrupt requests may occur during this interval but only

the interrupt request flag is recorded. If a certain inter-

rupt needs servicing within the service routine, the pro-

grammer may set the EMI bit and the corresponding bit

of the INTC to allow interrupt nesting. If the stack is full,

the interrupt request will not be acknowledged, even if

the related interrupt is enabled, until the SP is decre-

mented. If immediate service is desired, the stack must

be prevented from becoming full.

All these kinds of interrupt have a wake-up capability. As

an interrupt is serviced, a control transfer occurs by push-

ing the program counter onto the stack and then branch-

ing to subroutines at specified locations in the program

memory. Only the program counter is pushed onto the

stack. If the contents of the register and Status register

(STATUS) are altered by the interrupt service program

which may corrupt the desired control sequence, then the

programmer must save the contents first.

The internal Timer Counter 0 interrupt is initialized by set-

ting the Timer Counter 0 interrupt request flag (T0F; bit 5

of INTC), caused by a Timer Counter 0 overflow. When

the interrupt is enabled, and the stack is not full and the

T0F bit is set, a subroutine call to location 08H will occur.

The related interrupt request flag (T0F) will be reset and

the EMI bit cleared to disable further interrupts.

The Timer Counter 1 interrupt is operated in the same

manner as Timer Counter 0. The related interrupt con-

trol bits ET1I and T1F of the Timer Counter 1 are bit 3

and bit 6 of the INTC respectively.

During the execution of an interrupt subroutine, other in-

terrupt acknowledgments are held until the RETI in-

struction is executed or the EMI bit and the related

interrupt control bit are set to 1 (if the stack is not full). To

return from the interrupt subroutine, the RET or RETI in-

struction may be invoked. RETI will set the EMI bit to en-

able an interrupt service, but RET will not.

Interrupts occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In the case of simultaneous requests

the priorities in the following table apply. These can be

masked by resetting the EMI bit.

Interrupt Source

Priority

Vector

Timer Counter 0 overflow

1

08H

Timer Counter 1 overflow

2

0CH

The Timer Counter 0/1 interrupt request flag (T0F/T1F),

Enable Timer Counter 0/1 bit (ET0I/ET1I), Enable Mas-

ter Interrupt bit (EMI) constitute an interrupt control reg-

ister (INTC) which is located at 0BH in the data memory.

EMI, ET0I, ET1I are used to control the enabling/dis-

abling of interrupts. These bits prevent the requested in-

terrupt from being serviced. Once the interrupt request

flags (T0F, T1F) are set, they will remain in the INTC

register until the interrupts are serviced or cleared by a

software instruction.

It is recommended that a program does not use the

²CALL subroutine² within the interrupt subroutine. Be-

cause interrupts often occur in an unpredictable manner

or need to be serviced immediately in some applica-

tions, if only one stack is left and enabling the interrupt is

not well controlled, once the

²CALL subroutine² operates

in the interrupt subroutine, it may damage the original

control sequence.

Labels

Bits

Function

C0

C is set if an operation results in a carry during an addition operation or if a borrow does not take

place during a subtraction operation; otherwise C is cleared. Also it is affected by a rotate

through carry instruction.

AC

1

AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the

high nibble into the low nibble in subtraction; otherwise AC is cleared.

Z

2

Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.

OV

3

OV is set if an operation results in a carry into the highest-order bit but not a carry out of the high-

est-order bit, or vice versa; otherwise OV is cleared.

PD

4

PD is cleared by either a system power-up or executing the CLR WDT instruction. PD is set by

executing the HALT instruction.

TO

5

TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by

a WDT time-out.

¾

6~7

Unused bit, read as

²0²

Status register