CS5504 datasheet(15/24 Pages) CIRRUS

15 / 24 page

If the CS5504 is operated at a clock rate other

than 32.768 kHz, the filter characteristics, in-

cluding the comb filter zeros, will scale with the

operating clock frequency. Therefore, optimum

rejection of line frequency interference will oc-

cur with the CS5504 running at 32.768 kHz.

Anti-Alias Considerations for Spectral

Measurement Applications

Input frequencies greater than one half the out-

put word rate (CONV = 1) may be aliased by

the converter.

To prevent this, input signals

should be limited in frequency to no greater than

one half the output word rate of the converter

(when

CONV =1). Frequencies close to the modulator

sample rate (XIN/2) and multiples thereof may

also be aliased. If the signal source includes

spectral components above one half the output

word rate (when CONV = 1) these components

should be removed by means of low-pass filter-

ing prior to the A/D input to prevent aliasing.

Spectral components greater than one half the

output word rate on the VREF inputs (VREF+

and VREF-) may also be aliased. Filtering of the

reference voltage to remove these spectral com-

ponents from the reference voltage is desirable.

Crystal Oscillator

The CS5504 is designed to be operated using a

32.768 kHz "tuning fork" type crystal. One end

of the crystal should be connected to the XIN

input. The other end should be attached to

XOUT.

Short lead lengths should be used to

minimize stray capacitance.

Over the industrial temperature range (-40 to

+85

°C) the on-chip gate oscillator will oscillate

with other crystals in the range of 30 kHz to 53

kHz. The chip will operate with external clock

frequencies from 30 kHz to 330 kHz over the in-

dustrial temperature range.

The 32.768 kHz

crystal is normally specified as a time-keeping

crystal with tight specifications for both initial

frequency and for drift over temperature.

maintain excellent frequency stability, these

crystals are specified only over limited operating

temperature ranges (i.e. -10

°C to +60 °C) by the

manufacturers.

Applications of these crystals

with the CS5504 does not require tight initial

tolerance or low tempco drift. Therefore, a lower

cost crystal with looser initial tolerance and tem-

pco will generally be adequate for use with the

CS5504. Also check with the manufacturer

about wide temperature range application of

their standard crystals.

Generally, even those

crystals specified for limited temperature range

will operate over much larger ranges if fre-

quency stability over temperature is not a

requirement. The frequency stability can be as

bad as

±3000 ppm over the operating tempera-

ture range and still be typically better than the

line frequency (50 Hz or 60 Hz) stability over

cycle-to-cycle during the course of a day.

Serial Interface Logic

The digital filter in the CS5504 takes 1624 clock

cycles to compute an output word once a con-

version begins.

At the end of the conversion

cycle, the filter will attempt to update the serial

port. Two clock cycles prior to the update

DRDY will go high. When DRDY goes high

just prior to a port update it checks to see if the

port is either empty or unselected (CS = 1). If

the port is empty or unselected, the digital filter

will update the port with a new output word.

When new data is put into the port DRDY will

go low.

Reading Serial Data

SDATA is the output pin for the serial data.

When CS goes low after new data becomes

available (DRDY goes low), the SDATA pin

comes out of Hi-Z with the MSB data bit pre-

sent. SCLK is the input pin for the serial clock.

If the MSB data bit is on the SDATA pin, the

CS5504

DS126F1

CS5504

DS126F2

CS5504 Datasheet(PDF) 15 Page - Cirrus Logic

CS5504 Datasheet(HTML) 15 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL